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authorAndreas Regel <andreas.regel@newayselectronics.com>2018-01-09 08:07:52 (GMT)
committerAndreas Regel <andreas.regel@newayselectronics.com>2018-01-09 08:07:52 (GMT)
commitda7ff05881501450be84bc870fdb1931b7e57af2 (patch)
tree94217011b95c865fc33c20162e0013044a761d1a
parentfe88231028cc137b9e97ae1024ce8781244f3103 (diff)
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Remove default assignment from Translator::trVhdlType() declaration
-rw-r--r--src/classdef.cpp2
-rw-r--r--src/memberdef.cpp2
-rw-r--r--src/translator.h2
-rw-r--r--src/vhdldocgen.cpp6
4 files changed, 6 insertions, 6 deletions
diff --git a/src/classdef.cpp b/src/classdef.cpp
index 94d8035..f121e27 100644
--- a/src/classdef.cpp
+++ b/src/classdef.cpp
@@ -2474,7 +2474,7 @@ void ClassDef::writeMemberList(OutputList &ol)
QStrList sl;
if (lang==SrcLangExt_VHDL)
{
- sl.append(theTranslator->trVhdlType(md->getMemberSpecifiers())); //append vhdl type
+ sl.append(theTranslator->trVhdlType(md->getMemberSpecifiers(),TRUE)); //append vhdl type
}
else if (md->isFriend()) sl.append("friend");
else if (md->isRelated()) sl.append("related");
diff --git a/src/memberdef.cpp b/src/memberdef.cpp
index 36259c6..c9f9121 100644
--- a/src/memberdef.cpp
+++ b/src/memberdef.cpp
@@ -1978,7 +1978,7 @@ void MemberDef::getLabels(QStrList &sl,Definition *container) const
bool extractPrivate = Config_getBool(EXTRACT_PRIVATE);
if (optVhdl)
{
- sl.append(theTranslator->trVhdlType(getMemberSpecifiers()));
+ sl.append(theTranslator->trVhdlType(getMemberSpecifiers(),TRUE));
}
else
{
diff --git a/src/translator.h b/src/translator.h
index 377ad45..7ee49cf 100644
--- a/src/translator.h
+++ b/src/translator.h
@@ -583,7 +583,7 @@ class Translator
virtual QCString trDesignUnitIndex() = 0;
virtual QCString trDesignUnits() = 0;
virtual QCString trFunctionAndProc() = 0;
- virtual QCString trVhdlType(uint64 type,bool single=true) = 0;
+ virtual QCString trVhdlType(uint64 type,bool single) = 0;
virtual QCString trCustomReference(const char *name) = 0;
};
diff --git a/src/vhdldocgen.cpp b/src/vhdldocgen.cpp
index 40c0d46..fd5e4d7 100644
--- a/src/vhdldocgen.cpp
+++ b/src/vhdldocgen.cpp
@@ -1753,7 +1753,7 @@ void VhdlDocGen::writeVhdlDeclarations(MemberList* ml,
VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::GROUP,FALSE),0,FALSE,VhdlDocGen::GROUP);
VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::INSTANTIATION,FALSE),0,FALSE,VhdlDocGen::INSTANTIATION);
VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::ALIAS,FALSE),0,FALSE,VhdlDocGen::ALIAS);
- VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::MISCELLANEOUS),0,FALSE,VhdlDocGen::MISCELLANEOUS);
+ VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::MISCELLANEOUS,TRUE),0,FALSE,VhdlDocGen::MISCELLANEOUS);
// configurations must be added to global file definitions.
VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::CONFIG,FALSE),0,FALSE,VhdlDocGen::CONFIG);
@@ -2379,7 +2379,7 @@ bool VhdlDocGen::writeClassType( ClassDef *& cd,
OutputList &ol ,QCString & cname)
{
int id=cd->protection();
- QCString qcs = theTranslator->trVhdlType(id+2);
+ QCString qcs = theTranslator->trVhdlType(id+2,TRUE);
cname=VhdlDocGen::getClassName(cd);
ol.startBold();
ol.writeString(qcs.data());
@@ -3834,7 +3834,7 @@ void FlowChart::createSVG()
//const MemberDef *m=VhdlDocGen::getFlowMember();
//if (m)
- // fprintf(stderr,"\n creating flowchart : %s %s in file %s \n",theTranslator->trVhdlType(m->getMemberSpecifiers()),m->name().data(),m->getFileDef()->name().data());
+ // fprintf(stderr,"\n creating flowchart : %s %s in file %s \n",theTranslator->trVhdlType(m->getMemberSpecifiers(),TRUE),m->name().data(),m->getFileDef()->name().data());
QCString dir=" -o \""+ov+qcs+"\"";
ov+="/flow_design.dot";