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| author | Andreas Regel <andreas.regel@newayselectronics.com> | 2018-01-09 08:07:52 (GMT) |
|---|---|---|
| committer | Andreas Regel <andreas.regel@newayselectronics.com> | 2018-01-09 08:07:52 (GMT) |
| commit | da7ff05881501450be84bc870fdb1931b7e57af2 (patch) | |
| tree | 94217011b95c865fc33c20162e0013044a761d1a /src/classdef.cpp | |
| parent | fe88231028cc137b9e97ae1024ce8781244f3103 (diff) | |
| download | Doxygen-da7ff05881501450be84bc870fdb1931b7e57af2.zip Doxygen-da7ff05881501450be84bc870fdb1931b7e57af2.tar.gz Doxygen-da7ff05881501450be84bc870fdb1931b7e57af2.tar.bz2 | |
Remove default assignment from Translator::trVhdlType() declaration
Diffstat (limited to 'src/classdef.cpp')
| -rw-r--r-- | src/classdef.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/classdef.cpp b/src/classdef.cpp index 94d8035..f121e27 100644 --- a/src/classdef.cpp +++ b/src/classdef.cpp @@ -2474,7 +2474,7 @@ void ClassDef::writeMemberList(OutputList &ol) QStrList sl; if (lang==SrcLangExt_VHDL) { - sl.append(theTranslator->trVhdlType(md->getMemberSpecifiers())); //append vhdl type + sl.append(theTranslator->trVhdlType(md->getMemberSpecifiers(),TRUE)); //append vhdl type } else if (md->isFriend()) sl.append("friend"); else if (md->isRelated()) sl.append("related"); |