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| author | Andreas Regel <andreas.regel@newayselectronics.com> | 2017-12-05 14:35:16 (GMT) |
|---|---|---|
| committer | Andreas Regel <andreas.regel@newayselectronics.com> | 2018-01-08 13:10:52 (GMT) |
| commit | f1fea3603fa3e561d8f1efff5bc685e4484e7998 (patch) | |
| tree | 5364f559d7270be2b18eff8d96e62b2ef78d6edb /src/rtfgen.cpp | |
| parent | 6caac96a48e055807920f724d7de68f764e06441 (diff) | |
| download | Doxygen-f1fea3603fa3e561d8f1efff5bc685e4484e7998.zip Doxygen-f1fea3603fa3e561d8f1efff5bc685e4484e7998.tar.gz Doxygen-f1fea3603fa3e561d8f1efff5bc685e4484e7998.tar.bz2 | |
Add VHDL strings to Translator class and add german translations.
Diffstat (limited to 'src/rtfgen.cpp')
| -rw-r--r-- | src/rtfgen.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rtfgen.cpp b/src/rtfgen.cpp index 7fcfbb3..70a4c78 100644 --- a/src/rtfgen.cpp +++ b/src/rtfgen.cpp @@ -703,7 +703,7 @@ void RTFGenerator::endIndexSection(IndexSections is) } else if (vhdlOpt) { - t << "{\\tc \\v " << VhdlDocGen::trDesignUnitIndex() << "}"<< endl; + t << "{\\tc \\v " << theTranslator->trDesignUnitIndex() << "}"<< endl; } else { |