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author | albert-github <albert.tests@gmail.com> | 2018-03-29 12:37:52 (GMT) |
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committer | albert-github <albert.tests@gmail.com> | 2018-03-29 12:37:52 (GMT) |
commit | 36afe5e25c10dfd5a6208df7c8892eb2bb7498c5 (patch) | |
tree | 69fa5054e6b9df0586e50e18e8d1883cfb1d1e18 /src/vhdldocgen.cpp | |
parent | 7e2fcd305c8c9377aa958a3d812cc31bc81c0e32 (diff) | |
download | Doxygen-36afe5e25c10dfd5a6208df7c8892eb2bb7498c5.zip Doxygen-36afe5e25c10dfd5a6208df7c8892eb2bb7498c5.tar.gz Doxygen-36afe5e25c10dfd5a6208df7c8892eb2bb7498c5.tar.bz2 |
Better HTML output for VHDL Ports
Small alignment improvement of HTML output for VHDL Ports so that the mode will be in a separate column
Diffstat (limited to 'src/vhdldocgen.cpp')
-rw-r--r-- | src/vhdldocgen.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/vhdldocgen.cpp b/src/vhdldocgen.cpp index dcf7f42..6625d16 100644 --- a/src/vhdldocgen.cpp +++ b/src/vhdldocgen.cpp @@ -2096,19 +2096,21 @@ void VhdlDocGen::writeVHDLDeclaration(MemberDef* mdef,OutputList &ol, writeLink(mdef,ol); ol.docify(" "); - ol.insertMemberAlign(); if (mm==VhdlDocGen::GENERIC) { + ol.insertMemberAlign(); ol.startBold(); VhdlDocGen::formatString(largs,ol,mdef); ol.endBold(); } else { + ol.insertMemberAlignLeft(isAnonymous, false); ol.docify(" "); ol.startBold(); VhdlDocGen::formatString(ltype,ol,mdef); ol.endBold(); + ol.insertMemberAlign(); ol.docify(" "); VhdlDocGen::formatString(largs,ol,mdef); } @@ -2263,11 +2265,11 @@ void VhdlDocGen::writeVHDLDeclaration(MemberDef* mdef,OutputList &ol, ol.endMemberItem(); if (!mdef->briefDescription().isEmpty() && Config_getBool(BRIEF_MEMBER_DESC) /* && !annMemb */) { - QCString s=mdef->briefDescription(); - ol.startMemberDescription(mdef->anchor()); + QCString s=mdef->briefDescription(); + ol.startMemberDescription(mdef->anchor(), NULL, mm == VhdlDocGen::PORT); ol.generateDoc(mdef->briefFile(),mdef->briefLine(), - mdef->getOuterScope()?mdef->getOuterScope():d, - mdef,s.data(),TRUE,FALSE,0,TRUE,FALSE); + mdef->getOuterScope()?mdef->getOuterScope():d, + mdef,s.data(),TRUE,FALSE,0,TRUE,FALSE); if (detailsVisible) { ol.pushGeneratorState(); @@ -2364,7 +2366,7 @@ void VhdlDocGen::writeVHDLDeclarations(MemberList* ml,OutputList &ol, if (title) { - ol.startMemberHeader(title); + ol.startMemberHeader(title,type == VhdlDocGen::PORT ? 3 : 2); ol.parseText(title); ol.endMemberHeader(); ol.docify(" "); |