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| author | Andreas Regel <andreas.regel@newayselectronics.com> | 2018-01-09 08:07:52 (GMT) |
|---|---|---|
| committer | Andreas Regel <andreas.regel@newayselectronics.com> | 2018-01-09 08:07:52 (GMT) |
| commit | da7ff05881501450be84bc870fdb1931b7e57af2 (patch) | |
| tree | 94217011b95c865fc33c20162e0013044a761d1a /src/vhdldocgen.cpp | |
| parent | fe88231028cc137b9e97ae1024ce8781244f3103 (diff) | |
| download | Doxygen-da7ff05881501450be84bc870fdb1931b7e57af2.zip Doxygen-da7ff05881501450be84bc870fdb1931b7e57af2.tar.gz Doxygen-da7ff05881501450be84bc870fdb1931b7e57af2.tar.bz2 | |
Remove default assignment from Translator::trVhdlType() declaration
Diffstat (limited to 'src/vhdldocgen.cpp')
| -rw-r--r-- | src/vhdldocgen.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdldocgen.cpp b/src/vhdldocgen.cpp index 40c0d46..fd5e4d7 100644 --- a/src/vhdldocgen.cpp +++ b/src/vhdldocgen.cpp @@ -1753,7 +1753,7 @@ void VhdlDocGen::writeVhdlDeclarations(MemberList* ml, VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::GROUP,FALSE),0,FALSE,VhdlDocGen::GROUP); VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::INSTANTIATION,FALSE),0,FALSE,VhdlDocGen::INSTANTIATION); VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::ALIAS,FALSE),0,FALSE,VhdlDocGen::ALIAS); - VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::MISCELLANEOUS),0,FALSE,VhdlDocGen::MISCELLANEOUS); + VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::MISCELLANEOUS,TRUE),0,FALSE,VhdlDocGen::MISCELLANEOUS); // configurations must be added to global file definitions. VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,nd,fd,gd,theTranslator_vhdlType(VhdlDocGen::CONFIG,FALSE),0,FALSE,VhdlDocGen::CONFIG); @@ -2379,7 +2379,7 @@ bool VhdlDocGen::writeClassType( ClassDef *& cd, OutputList &ol ,QCString & cname) { int id=cd->protection(); - QCString qcs = theTranslator->trVhdlType(id+2); + QCString qcs = theTranslator->trVhdlType(id+2,TRUE); cname=VhdlDocGen::getClassName(cd); ol.startBold(); ol.writeString(qcs.data()); @@ -3834,7 +3834,7 @@ void FlowChart::createSVG() //const MemberDef *m=VhdlDocGen::getFlowMember(); //if (m) - // fprintf(stderr,"\n creating flowchart : %s %s in file %s \n",theTranslator->trVhdlType(m->getMemberSpecifiers()),m->name().data(),m->getFileDef()->name().data()); + // fprintf(stderr,"\n creating flowchart : %s %s in file %s \n",theTranslator->trVhdlType(m->getMemberSpecifiers(),TRUE),m->name().data(),m->getFileDef()->name().data()); QCString dir=" -o \""+ov+qcs+"\""; ov+="/flow_design.dot"; |