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| author | Dimitri van Heesch <dimitri@stack.nl> | 2015-04-27 19:04:45 (GMT) |
|---|---|---|
| committer | Adrian Negreanu <adrian.m.negreanu@intel.com> | 2015-05-15 16:06:04 (GMT) |
| commit | 3eed7a5c5b330736b508c722c9614c774a678ef1 (patch) | |
| tree | bd732e7e13c05f9089315b83c0790fa4b7e44737 /src | |
| parent | 2c679e7d39144dadef2e9fd25772f0e41586e18b (diff) | |
| download | Doxygen-3eed7a5c5b330736b508c722c9614c774a678ef1.zip Doxygen-3eed7a5c5b330736b508c722c9614c774a678ef1.tar.gz Doxygen-3eed7a5c5b330736b508c722c9614c774a678ef1.tar.bz2 | |
Various VHDL related fixes
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdldocgen.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/vhdldocgen.cpp b/src/vhdldocgen.cpp index 2b92d40..029d0bd 100644 --- a/src/vhdldocgen.cpp +++ b/src/vhdldocgen.cpp @@ -2212,6 +2212,19 @@ void VhdlDocGen::writeVHDLDeclaration(MemberDef* mdef,OutputList &ol, ol.insertMemberAlign(); VhdlDocGen::formatString(ltype,ol,mdef); break; + case VhdlDocGen::RECORD: + case VhdlDocGen::UNITS: + writeLink(mdef,ol); + ol.docify(" "); + ol.startBold(); + if (ltype.isEmpty()) { + ol.docify(" "); + } + ol.insertMemberAlign(); + if (!ltype.isEmpty()) + VhdlDocGen::formatString(ltype,ol,mdef); + ol.endBold(); + break; case VhdlDocGen::TYPE: bRec=largs.stripPrefix("record") ; bUnit=largs.stripPrefix("units") ; |