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| author | powARman <andreas.regel@gmx.de> | 2020-08-03 18:02:45 (GMT) |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-03 18:02:45 (GMT) |
| commit | 5e293b201f46bd98695bcc92ce2ecaa1f2b15c54 (patch) | |
| tree | 80e41cf29284faf03b0ce9aa9de16f9a3e7a6ad3 /vhdlparser/vhdlparser.jj | |
| parent | 97b6582daef5028fd3077a7fc29bd94b393f7ae1 (diff) | |
| download | Doxygen-5e293b201f46bd98695bcc92ce2ecaa1f2b15c54.zip Doxygen-5e293b201f46bd98695bcc92ce2ecaa1f2b15c54.tar.gz Doxygen-5e293b201f46bd98695bcc92ce2ecaa1f2b15c54.tar.bz2 | |
Vhdl improvements (ALIAS, translation) (#7813)
* Support VHDL alias constructs.
* Translate class to "Design Unit" for VHDL.
* Fix compile error
* Add new function trDesignUnitDocumentation() to translator.
Adapt english and german translation to use the new function.
Co-authored-by: Andreas Regel <andreas.regel@newayselectronics.com>
Diffstat (limited to 'vhdlparser/vhdlparser.jj')
| -rwxr-xr-x | vhdlparser/vhdlparser.jj | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vhdlparser/vhdlparser.jj b/vhdlparser/vhdlparser.jj index 007bd5b..177b5f4 100755 --- a/vhdlparser/vhdlparser.jj +++ b/vhdlparser/vhdlparser.jj @@ -143,7 +143,7 @@ TOKEN [IGNORE_CASE] : <ABS_T: "abs"> | <ACCESS_T: "access"> | <AFTER_T: "after"> -| <ALIAS_T: "alias"> +| <ALIAS_T: "alias"> {parser->outlineParser()->setLineParsed(ALIAS_T);} | <ALL_T: "all"> | <AND_T: "and"> | <ARCHITECTURE_T: "architecture"> {parser->outlineParser()->setLineParsed(ARCHITECTURE_T);} |