summaryrefslogtreecommitdiffstats
path: root/src/vhdldocgen.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/vhdldocgen.cpp')
-rw-r--r--src/vhdldocgen.cpp771
1 files changed, 254 insertions, 517 deletions
diff --git a/src/vhdldocgen.cpp b/src/vhdldocgen.cpp
index 4619b7a..7afc832 100644
--- a/src/vhdldocgen.cpp
+++ b/src/vhdldocgen.cpp
@@ -24,10 +24,10 @@
#include <stdlib.h>
#include <assert.h>
#include <string.h>
+#include <map>
#include <qcstring.h>
#include <qfileinfo.h>
#include <qcstringlist.h>
-#include <qmap.h>
/* --------------------------------------------------------------- */
@@ -55,23 +55,18 @@
#include "filename.h"
#include "membergroup.h"
#include "memberdef.h"
+#include "membername.h"
#include "plantuml.h"
#include "vhdljjparser.h"
#include "VhdlParser.h"
-#include "vhdlcode.h"
+//#include "vhdlcode.h"
#include "plantuml.h"
//#define DEBUGFLOW
#define theTranslator_vhdlType theTranslator->trVhdlType
-static QDict<QCString> g_vhdlKeyDict0(17,FALSE);
-static QDict<QCString> g_vhdlKeyDict1(17,FALSE);
-static QDict<QCString> g_vhdlKeyDict2(17,FALSE);
-static QDict<QCString> g_vhdlKeyDict3(17,FALSE);
-
static void initUCF(Entry* root,const char* type,QCString & qcs,int line,QCString & fileName,QCString & brief);
static void writeUCFLink(const MemberDef* mdef,OutputList &ol);
-static void assignBinding(VhdlConfNode* conf);
-static void addInstance(ClassDef* entity, ClassDef* arch, ClassDef *inst,
+static void addInstance(ClassDefMutable* entity, ClassDefMutable* arch, ClassDefMutable *inst,
const std::shared_ptr<Entry> &cur);
//---------- create svg -------------------------------------------------------------
@@ -179,10 +174,8 @@ static void createSVG()
// Brief descriptions for entities are shown too.
void VhdlDocGen::writeOverview()
{
- ClassSDict::Iterator cli(*Doxygen::classSDict);
- ClassDef *cd;
bool found=FALSE;
- for ( ; (cd=cli.current()) ; ++cli )
+ for (const auto &cd : *Doxygen::classLinkedMap)
{
if ((VhdlDocGen::VhdlClasses)cd->protection()==VhdlDocGen::ENTITYCLASS )
{
@@ -200,20 +193,20 @@ void VhdlDocGen::writeOverview()
if (!f.open(IO_WriteOnly))
{
- fprintf(stderr,"Warning: Cannot open file %s for writing\n",fileName.data());
+ err("Warning: Cannot open file %s for writing\n",fileName.data());
return;
}
startDot(t);
- for (cli.toFirst() ; (cd=cli.current()) ; ++cli )
+ for (const auto &cd : *Doxygen::classLinkedMap)
{
if ((VhdlDocGen::VhdlClasses)cd->protection()!=VhdlDocGen::ENTITYCLASS )
{
continue;
}
- QList<MemberDef>* port= getPorts(cd);
+ QList<MemberDef>* port= getPorts(cd.get());
if (port==0)
{
continue;
@@ -226,30 +219,23 @@ void VhdlDocGen::writeOverview()
}
startTable(t,cd->name());
- writeClassToDot(t,cd);
+ writeClassToDot(t,cd.get());
writeTable(port,t);
endTable(t);
- // writeVhdlPortToolTip(t,port,cd);
- writeVhdlEntityToolTip(t,cd);
+ writeVhdlEntityToolTip(t,cd.get());
delete port;
- BaseClassList *bl=cd->baseClasses();
- if (bl)
+ for (const auto &bcd : cd->baseClasses())
{
- BaseClassListIterator bcli(*bl);
- BaseClassDef *bcd;
- for ( ; (bcd=bcli.current()) ; ++bcli )
- {
- ClassDef *bClass=bcd->classDef;
- QCString dotn=cd->name()+":";
- dotn+=cd->name();
- QCString csc=bClass->name()+":";
- csc+=bClass->name();
- // fprintf(stderr,"\n <%s| %s>",dotn.data(),csc.data());
- writeVhdlDotLink(t,dotn,csc,0);
- }
- }// if bl
+ ClassDef *bClass=bcd.classDef;
+ QCString dotn=cd->name()+":";
+ dotn+=cd->name();
+ QCString csc=bClass->name()+":";
+ csc+=bClass->name();
+ // fprintf(stderr,"\n <%s| %s>",dotn.data(),csc.data());
+ writeVhdlDotLink(t,dotn,csc,0);
+ }
}// for
endDot(t);
@@ -568,11 +554,8 @@ VhdlDocGen::~VhdlDocGen()
{
}
-void VhdlDocGen::init()
-{
-
// vhdl keywords included VHDL 2008
-const char* g_vhdlKeyWordMap0[] =
+static const std::set< std::string > g_vhdlKeyWordSet0 =
{
"abs","access","after","alias","all","and","architecture","array","assert","assume","assume_guarantee","attribute",
"begin","block","body","buffer","bus",
@@ -593,100 +576,57 @@ const char* g_vhdlKeyWordMap0[] =
"unaffected","units","until","use",
"variable","vmode","vprop","vunit",
"wait","when","while","with",
- "xor","xnor",
- 0
+ "xor","xnor"
};
// type
-const char* g_vhdlKeyWordMap1[] =
+static const std::set< std::string> g_vhdlKeyWordSet1 =
{
"natural","unsigned","signed","string","boolean", "bit","bit_vector","character",
"std_ulogic","std_ulogic_vector","std_logic","std_logic_vector","integer",
- "real","float","ufixed","sfixed","time","positive",0
+ "real","float","ufixed","sfixed","time","positive"
};
// logic
-const char* g_vhdlKeyWordMap2[] =
+static const std::set< std::string > g_vhdlKeyWordSet2 =
{
- "abs","and","or","not","mod", "xor","rem","xnor","ror","rol","sla",
- "sll",0
+ "abs","and","or","not","mod","xor","rem","xnor","ror","rol","sla","sll"
};
// predefined attributes
-const char* g_vhdlKeyWordMap3[] =
+static const std::set< std::string > g_vhdlKeyWordSet3 =
{
-"base","left","right","high","low","ascending",
-"image","value","pos","val","succ","pred","leftof","rightof","left","right","high","low",
-"range","reverse_range","length","ascending","delayed","stable","quiet","transaction","event",
-"active","last_event","last_active","last_value","driving","driving_value","simple_name","instance_name","path_name",0
+ "base","left","right","high","low","ascending",
+ "image","value","pos","val","succ","pred","leftof","rightof","left","right","high","low",
+ "range","reverse_range","length","ascending","delayed","stable","quiet","transaction","event",
+ "active","last_event","last_active","last_value","driving","driving_value","simple_name","instance_name","path_name"
};
- int j=0;
- g_vhdlKeyDict0.setAutoDelete(TRUE);
- g_vhdlKeyDict1.setAutoDelete(TRUE);
- g_vhdlKeyDict2.setAutoDelete(TRUE);
- g_vhdlKeyDict3.setAutoDelete(TRUE);
-
- while (g_vhdlKeyWordMap0[j])
- {
- g_vhdlKeyDict0.insert(g_vhdlKeyWordMap0[j],
- new QCString(g_vhdlKeyWordMap0[j]));
- j++;
- }
-
- j=0;
- while (g_vhdlKeyWordMap1[j])
- {
- g_vhdlKeyDict1.insert(g_vhdlKeyWordMap1[j],
- new QCString(g_vhdlKeyWordMap1[j]));
- j++;
- }
-
- j=0;
- while (g_vhdlKeyWordMap2[j])
- {
- g_vhdlKeyDict2.insert(g_vhdlKeyWordMap2[j],
- new QCString(g_vhdlKeyWordMap2[j]));
- j++;
- }
-
- j=0;
- while (g_vhdlKeyWordMap3[j])
- {
- g_vhdlKeyDict3.insert(g_vhdlKeyWordMap3[j],
- new QCString(g_vhdlKeyWordMap3[j]));
- j++;
- }
-
-}// buildKeyMap
+void VhdlDocGen::init()
+{
+}
/*!
* returns the color of a keyword
*/
-
-QCString* VhdlDocGen::findKeyWord(const QCString& tmp)
+const char* VhdlDocGen::findKeyWord(const QCString& kw)
{
- static QCString vhdlkeyword("vhdlkeyword");
- static QCString vhdltype("keywordtype");
- static QCString vhdllogic("vhdllogic");
- static QCString preprocessor("keywordflow");
+ std::string word=kw.lower().str();
- QCString word=tmp.lower();
+ if (word.empty()) return 0;
- if (word.isEmpty() || word.at(0)=='\0') return 0;
+ if (g_vhdlKeyWordSet0.find(word)!=g_vhdlKeyWordSet0.end())
+ return "keywordflow";
- if (g_vhdlKeyDict0.find(word))
- return &preprocessor;
+ if (g_vhdlKeyWordSet1.find(word)!=g_vhdlKeyWordSet1.end())
+ return "keywordtype";
- if (g_vhdlKeyDict1.find(word))
- return &vhdltype;
+ if (g_vhdlKeyWordSet2.find(word)!=g_vhdlKeyWordSet2.end())
+ return "vhdllogic";
- if (g_vhdlKeyDict2.find(word))
- return &vhdllogic;
-
- if (g_vhdlKeyDict3.find(word))
- return &vhdlkeyword;
+ if (g_vhdlKeyWordSet3.find(word)!=g_vhdlKeyWordSet3.end())
+ return "vhdlkeyword";
return 0;
}
@@ -694,26 +634,17 @@ QCString* VhdlDocGen::findKeyWord(const QCString& tmp)
ClassDef *VhdlDocGen::getClass(const char *name)
{
if (name==0 || name[0]=='\0') return 0;
-
- ClassDef *cd=0;
- QCString temp(name);
- //temp=temp.lower();
- temp=temp.stripWhiteSpace();
- cd= Doxygen::classSDict->find(temp.data());
- return cd;
+ return Doxygen::classLinkedMap->find(QCString(name).stripWhiteSpace());
}
ClassDef* VhdlDocGen::getPackageName(const QCString & name)
{
- ClassDef* cd=0;
- cd=getClass(name);
-
- return cd;
+ return getClass(name);
}
-static QMap<QCString,MemberDef*> varMap;
-static QList<ClassDef> qli;
-static QMap<ClassDef*,QList<ClassDef> > packages;
+static std::map<std::string,MemberDef*> g_varMap;
+static std::vector<ClassDef*> g_classList;
+static std::map<ClassDef*,std::vector<ClassDef*> > g_packages;
MemberDef* VhdlDocGen::findMember(const QCString& className, const QCString& memName)
{
@@ -768,42 +699,41 @@ MemberDef* VhdlDocGen::findMember(const QCString& className, const QCString& mem
Definition *d = cd->getOuterScope();
QCString tt=d->name();
- ClassDef *ecd =getClass(tt);
- if (!ecd)
+ ClassDef *acd =getClass(tt);
+ if (!acd)
{
tt=tt.upper();
- ecd =getClass(tt);
+ acd =getClass(tt);
}
- if (!ecd)
+ if (!acd)
{
tt=tt.lower();
- ecd =getClass(tt);
+ acd =getClass(tt);
}
- if (ecd) //d && d->definitionType()==Definition::TypeClass)
+ if (acd) //d && d->definitionType()==Definition::TypeClass)
{
- if(!packages.contains(ecd))
+ if(g_packages.find(acd)==g_packages.end())
{
- VhdlDocGen::findAllPackages(ecd);
+ VhdlDocGen::findAllPackages(acd);
}
}
}
else
{
ecd=cd;
- if (!packages.contains(ecd)) VhdlDocGen::findAllPackages(ecd);
+ if (g_packages.find(ecd)==g_packages.end()) VhdlDocGen::findAllPackages(ecd);
}
if (ecd)
{
- QMap<ClassDef*,QList<ClassDef> >::Iterator cList=packages.find(ecd);
- if (cList!=packages.end())
+ auto cList_it = g_packages.find(ecd);
+ if (cList_it!=g_packages.end())
{
- QList<ClassDef> mlist=cList.data();
- for (uint j=0;j<mlist.count();j++)
+ for (const auto &cdp : cList_it->second)
{
- mdef=VhdlDocGen::findMemberDef(mlist.at(j),memName,MemberListType_variableMembers);
+ mdef=VhdlDocGen::findMemberDef(cdp,memName,MemberListType_variableMembers);
if (mdef) return mdef;
- mdef=VhdlDocGen::findMemberDef(mlist.at(j),memName,MemberListType_pubMethods);
+ mdef=VhdlDocGen::findMemberDef(cdp,memName,MemberListType_pubMethods);
if (mdef) return mdef;
}
}
@@ -823,21 +753,21 @@ MemberDef* VhdlDocGen::findMemberDef(ClassDef* cd,const QCString& key,MemberList
QCString keyType=cd->symbolName()+"@"+key;
//printf("\n %s | %s | %s",cd->symbolName().data(),key.data(,),keyType.data());
- QMap<QCString, MemberDef*>::Iterator it =varMap.find(keyType);
- if (it.key())
+ auto it = g_varMap.find(keyType.str());
+ if (it!=g_varMap.end())
{
- md=it.data();
+ md=it->second;
if (md)
{
return md;
}
}
- if (qli.contains(cd))
+ if (std::find(g_classList.begin(),g_classList.end(),cd)!=g_classList.end())
{
return 0;
}
ml=cd->getMemberList(type);
- qli.append(cd);
+ g_classList.push_back(cd);
if (!ml)
{
return 0;
@@ -849,16 +779,15 @@ MemberDef* VhdlDocGen::findMemberDef(ClassDef* cd,const QCString& key,MemberList
for (fmni.toFirst();(md=fmni.current());++fmni)
{
QCString tkey=cd->symbolName()+"@"+md->name();
- if (varMap.contains(tkey))
+ if (g_varMap.find(tkey.str())==g_varMap.end())
{
- continue;
+ g_varMap.insert({tkey.str(),md});
}
- varMap.insert(tkey.data(),md);
}
- it=varMap.find(keyType.data());
- if (it.key())
+ it=g_varMap.find(keyType.str());
+ if (it!=g_varMap.end())
{
- md=it.data();
+ md=it->second;
if (md)
{
return md;
@@ -873,8 +802,8 @@ MemberDef* VhdlDocGen::findMemberDef(ClassDef* cd,const QCString& key,MemberList
void VhdlDocGen::findAllPackages( ClassDef *cdef)
{
- QList<ClassDef> cList;
- if (packages.contains(cdef)) return;
+ if (g_packages.find(cdef)!=g_packages.end()) return;
+ std::vector<ClassDef*> cList;
MemberList *mem=cdef->getMemberList(MemberListType_variableMembers);
MemberDef *md;
@@ -888,9 +817,9 @@ void VhdlDocGen::findAllPackages( ClassDef *cdef)
ClassDef* cd=VhdlDocGen::getPackageName(md->name());
if (cd)
{
- cList.append(cd);
+ cList.push_back(cd);
VhdlDocGen::findAllPackages(cd);
- packages.insert(cdef,cList);
+ g_packages.insert({cdef,cList});
}
}
}//for
@@ -1040,12 +969,10 @@ void VhdlDocGen::writeInlineClassLink(const ClassDef* cd ,OutputList& ol)
*/
void VhdlDocGen::findAllArchitectures(QList<QCString>& qll,const ClassDef *cd)
{
- ClassDef *citer;
- ClassSDict::Iterator cli(*Doxygen::classSDict);
- for ( ; (citer=cli.current()) ; ++cli )
+ for (const auto &citer : *Doxygen::classLinkedMap)
{
QCString jj=citer->className();
- if (cd != citer && jj.contains('-')!=-1)
+ if (cd != citer.get() && jj.contains('-')!=-1)
{
QCStringList ql=QCStringList::split("-",jj);
QCString temp=ql[1];
@@ -1058,13 +985,10 @@ void VhdlDocGen::findAllArchitectures(QList<QCString>& qll,const ClassDef *cd)
}// for
}//findAllArchitectures
-ClassDef* VhdlDocGen::findArchitecture(const ClassDef *cd)
+const ClassDef* VhdlDocGen::findArchitecture(const ClassDef *cd)
{
- ClassDef *citer;
QCString nn=cd->name();
- ClassSDict::Iterator cli(*Doxygen::classSDict);
-
- for ( ; (citer=cli.current()) ; ++cli )
+ for (const auto &citer : *Doxygen::classLinkedMap)
{
QCString jj=citer->name();
QCStringList ql=QCStringList::split(":",jj);
@@ -1072,7 +996,7 @@ ClassDef* VhdlDocGen::findArchitecture(const ClassDef *cd)
{
if (ql[0]==nn )
{
- return citer;
+ return citer.get();
}
}
}
@@ -1154,7 +1078,6 @@ void VhdlDocGen::parseFuncProto(const char* text,QCString& name,QCString& ret,bo
}
else
{
- QCString s1(text);
s1=s1.stripWhiteSpace();
int i=s1.find("(",0,FALSE);
int s=s1.find(QRegExp("[ \\t]"));
@@ -1274,7 +1197,6 @@ void VhdlDocGen::writeFormatString(const QCString& s,OutputList&ol,const MemberD
QRegExp reg("[\\[\\]\\.\\/\\:\\<\\>\\:\\s\\,\\;\\'\\+\\-\\*\\|\\&\\=\\(\\)\"]");
QCString qcs = s;
qcs+=QCString(" ");// parsing the last sign
- QCString *ss;
QCString find=qcs;
QCString temp=qcs;
char buf[2];
@@ -1291,7 +1213,7 @@ void VhdlDocGen::writeFormatString(const QCString& s,OutputList&ol,const MemberD
{
find=find.left(j);
buf[0]=temp[j];
- ss=VhdlDocGen::findKeyWord(find);
+ const char *ss=VhdlDocGen::findKeyWord(find);
bool k=isNumber(find); // is this a number
if (k)
{
@@ -1301,7 +1223,7 @@ void VhdlDocGen::writeFormatString(const QCString& s,OutputList&ol,const MemberD
}
else if (j != 0 && ss)
{
- startFonts(find,ss->data(),ol);
+ startFonts(find,ss,ol);
}
else
{
@@ -1421,7 +1343,7 @@ void VhdlDocGen::formatString(const QCString &s, OutputList& ol,const MemberDef*
void VhdlDocGen::writeProcedureProto(OutputList& ol,const ArgumentList &al,const MemberDef* mdef)
{
bool sem=FALSE;
- int len=al.size();
+ size_t len=al.size();
ol.docify("( ");
if (len > 2)
{
@@ -1437,11 +1359,11 @@ void VhdlDocGen::writeProcedureProto(OutputList& ol,const ArgumentList &al,const
nn+=": ";
QCString defval = arg.defval;
- QCString *str=VhdlDocGen::findKeyWord(defval);
+ const char *str=VhdlDocGen::findKeyWord(defval);
defval+=" ";
if (str)
{
- startFonts(defval,str->data(),ol);
+ startFonts(defval,str,ol);
}
else
{
@@ -1477,7 +1399,7 @@ void VhdlDocGen::writeFunctionProto(OutputList& ol,const ArgumentList &al,const
{
if (!al.hasParameters()) return;
bool sem=FALSE;
- int len=al.size();
+ size_t len=al.size();
ol.startBold();
ol.docify(" ( ");
ol.endBold();
@@ -1502,7 +1424,7 @@ void VhdlDocGen::writeFunctionProto(OutputList& ol,const ArgumentList &al,const
}
if (!att.isEmpty())
{
- QCString *str=VhdlDocGen::findKeyWord(att);
+ const char *str=VhdlDocGen::findKeyWord(att);
att+=" ";
if (str)
VhdlDocGen::formatString(att,ol,mdef);
@@ -1516,7 +1438,7 @@ void VhdlDocGen::writeFunctionProto(OutputList& ol,const ArgumentList &al,const
QCString w=ss.stripWhiteSpace();//.upper();
startFonts(nn,"vhdlchar",ol);
startFonts("in ","stringliteral",ol);
- QCString *str=VhdlDocGen::findKeyWord(ss);
+ const char *str=VhdlDocGen::findKeyWord(ss);
if (str)
VhdlDocGen::formatString(w,ol,mdef);
else
@@ -1586,7 +1508,7 @@ bool VhdlDocGen::writeFuncProcDocu(
//bool sem=FALSE;
ol.enableAll();
- int index=al.size();
+ size_t index=al.size();
if (index==0)
{
ol.docify(" ( ) ");
@@ -1719,7 +1641,7 @@ void VhdlDocGen::writeVhdlDeclarations(const MemberList* ml,
}
-void VhdlDocGen::correctMemberProperties(MemberDef *md)
+void VhdlDocGen::correctMemberProperties(MemberDefMutable *md)
{
if (qstrcmp(md->argsString(),"package")==0)
{
@@ -1769,7 +1691,7 @@ void VhdlDocGen::correctMemberProperties(MemberDef *md)
/* writes a vhdl type documentation */
bool VhdlDocGen::writeVHDLTypeDocumentation(const MemberDef* mdef, const Definition *d, OutputList &ol)
{
- const ClassDef *cd=dynamic_cast<const ClassDef*>(d);
+ const ClassDef *cd=toClassDef(d);
bool hasParams = FALSE;
if (cd==0) return hasParams;
@@ -1851,7 +1773,7 @@ bool VhdlDocGen::writeVHDLTypeDocumentation(const MemberDef* mdef, const Definit
return hasParams;
}
-void VhdlDocGen::writeTagFile(MemberDef *mdef,FTextStream &tagFile)
+void VhdlDocGen::writeTagFile(MemberDefMutable *mdef,FTextStream &tagFile)
{
tagFile << " <member kind=\"";
if (VhdlDocGen::isGeneric(mdef)) tagFile << "generic";
@@ -1879,7 +1801,7 @@ void VhdlDocGen::writeTagFile(MemberDef *mdef,FTextStream &tagFile)
tagFile << "\">" << endl;
tagFile << " <type>" << convertToXML(mdef->typeString()) << "</type>" << endl;
tagFile << " <name>" << convertToXML(mdef->name()) << "</name>" << endl;
- tagFile << " <anchorfile>" << convertToXML(mdef->getOutputFileBase()+Doxygen::htmlFileExtension) << "</anchorfile>" << endl;
+ tagFile << " <anchorfile>" << convertToXML(mdef->getOutputFileBase()) << Doxygen::htmlFileExtension << "</anchorfile>" << endl;
tagFile << " <anchor>" << convertToXML(mdef->anchor()) << "</anchor>" << endl;
if (VhdlDocGen::isVhdlFunction(mdef))
@@ -1895,7 +1817,7 @@ void VhdlDocGen::writeTagFile(MemberDef *mdef,FTextStream &tagFile)
/* writes a vhdl type declaration */
-void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
+void VhdlDocGen::writeVHDLDeclaration(const MemberDefMutable* mdef,OutputList &ol,
const ClassDef *cd,const NamespaceDef *nd,const FileDef *fd,const GroupDef *gd,
bool /*inGroup*/)
{
@@ -1956,9 +1878,10 @@ void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
}
// *** write type
/*VHDL CHANGE */
- bool bRec,bUnit;
+
QCString ltype(mdef->typeString());
QCString largs(mdef->argsString());
+
ClassDef *kl=0;
const ArgumentList &al = mdef->argumentList();
QCString nn;
@@ -2014,7 +1937,7 @@ void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
ol.insertMemberAlign();
if (largs=="context")
{
- VhdlDocGen::writeRecorUnit(ltype,ol,mdef);
+ VhdlDocGen::writeRecordUnit(ltype,largs,ol,mdef);
}
break;
@@ -2079,7 +2002,6 @@ void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
ol.insertMemberAlign();
ol.docify(" ");
-
ol.startBold();
ol.docify(ltype);
ol.endBold();
@@ -2128,6 +2050,7 @@ void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
case VhdlDocGen::SHAREDVARIABLE:
case VhdlDocGen::VFILE:
case VhdlDocGen::GROUP:
+ case VhdlDocGen::TYPE:
writeLink(mdef,ol);
ol.docify(" ");
ol.insertMemberAlign();
@@ -2135,32 +2058,7 @@ void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
break;
case VhdlDocGen::RECORD:
case VhdlDocGen::UNITS:
- writeLink(mdef,ol);
- ol.docify(" ");
- ol.startBold();
- if (ltype.isEmpty()) {
- ol.docify(" ");
- }
- ol.insertMemberAlign();
- if (!ltype.isEmpty())
- VhdlDocGen::formatString(ltype,ol,mdef);
- ol.endBold();
- break;
- case VhdlDocGen::TYPE:
- bRec=largs.stripPrefix("record") ;
- bUnit=largs.stripPrefix("units") ;
- ol.startBold();
- if (bRec) ol.docify("record: ");
- if (bUnit) ol.docify("units: ");
- writeLink(mdef,ol);
- ol.insertMemberAlign();
- if (!bRec && !bUnit) VhdlDocGen::formatString(ltype,ol,mdef);
- if (bUnit) ol.lineBreak();
- if (bRec || bUnit)
- {
- writeRecorUnit(largs,ol,mdef);
- }
- ol.endBold();
+ writeRecordUnit(largs,ltype,ol,mdef);
break;
default: break;
@@ -2191,8 +2089,9 @@ void VhdlDocGen::writeVHDLDeclaration(const MemberDef* mdef,OutputList &ol,
QCString s=mdef->briefDescription();
ol.startMemberDescription(mdef->anchor(), NULL, mm == VhdlDocGen::PORT);
ol.generateDoc(mdef->briefFile(),mdef->briefLine(),
- mdef->getOuterScope()?mdef->getOuterScope():d,
- mdef,s.data(),TRUE,FALSE,0,TRUE,FALSE);
+ mdef->getOuterScope()?mdef->getOuterScope():d,
+ mdef,s.data(),TRUE,FALSE,
+ 0,TRUE,FALSE,Config_getBool(MARKDOWN_SUPPORT));
if (detailsVisible)
{
ol.pushGeneratorState();
@@ -2224,32 +2123,34 @@ void VhdlDocGen::writePlainVHDLDeclarations(
const ClassDef *cd,const NamespaceDef *nd,const FileDef *fd,const GroupDef *gd,int specifier)
{
- SDict<QCString> pack(1009);
- pack.setAutoDelete(TRUE);
+ StringSet pack;
bool first=TRUE;
- MemberDef *md;
+ MemberDef *imd;
MemberListIterator mli(*mlist);
- for ( ; (md=mli.current()); ++mli )
+ for ( ; (imd=mli.current()); ++mli )
{
- int mems=md->getMemberSpecifiers();
- if (md->isBriefSectionVisible() && (mems==specifier) && (mems!=VhdlDocGen::LIBRARY) )
- {
- if (first) { ol.startMemberList();first=FALSE; }
- VhdlDocGen::writeVHDLDeclaration(md,ol,cd,nd,fd,gd,FALSE);
- } //if
- else if (md->isBriefSectionVisible() && (mems==specifier))
+ MemberDefMutable *md = toMemberDefMutable(imd);
+ if (md)
{
- if (!pack.find(md->name().data()))
+ int mems=md->getMemberSpecifiers();
+ if (md->isBriefSectionVisible() && (mems==specifier) && (mems!=VhdlDocGen::LIBRARY) )
{
- if (first) ol.startMemberList(),first=FALSE;
+ if (first) { ol.startMemberList();first=FALSE; }
VhdlDocGen::writeVHDLDeclaration(md,ol,cd,nd,fd,gd,FALSE);
- pack.append(md->name().data(),new QCString(md->name().data()));
- }
+ } //if
+ else if (md->isBriefSectionVisible() && (mems==specifier))
+ {
+ if (pack.find(md->name().str())==pack.end())
+ {
+ if (first) ol.startMemberList(),first=FALSE;
+ VhdlDocGen::writeVHDLDeclaration(md,ol,cd,nd,fd,gd,FALSE);
+ pack.insert(md->name().str());
+ }
+ } //if
} //if
} //for
if (!first) ol.endMemberList();
- pack.clear();
}//plainDeclaration
static bool membersHaveSpecificType(const MemberList *ml,uint64 type)
@@ -2264,17 +2165,11 @@ static bool membersHaveSpecificType(const MemberList *ml,uint64 type)
return TRUE;
}
}
- if (ml->getMemberGroupList())
+ for (const auto &mg : ml->getMemberGroupList())
{
- MemberGroupListIterator mgli(*ml->getMemberGroupList());
- MemberGroup *mg;
- while ((mg=mgli.current()))
+ if (mg->members())
{
- if (mg->members())
- {
- if (membersHaveSpecificType(mg->members(),type)) return TRUE;
- }
- ++mgli;
+ if (membersHaveSpecificType(mg->members(),type)) return TRUE;
}
}
return FALSE;
@@ -2296,41 +2191,37 @@ void VhdlDocGen::writeVHDLDeclarations(const MemberList* ml,OutputList &ol,
if (subtitle && subtitle[0]!=0)
{
ol.startMemberSubtitle();
- ol.generateDoc("[generated]",-1,0,0,subtitle,FALSE,FALSE,0,TRUE,FALSE);
+ ol.generateDoc("[generated]",-1,0,0,subtitle,FALSE,FALSE,
+ 0,TRUE,FALSE,Config_getBool(MARKDOWN_SUPPORT));
ol.endMemberSubtitle();
} //printf("memberGroupList=%p\n",memberGroupList);
VhdlDocGen::writePlainVHDLDeclarations(ml,ol,cd,nd,fd,gd,type);
- if (ml->getMemberGroupList())
+ for (const auto &mg : ml->getMemberGroupList())
{
- MemberGroupListIterator mgli(*ml->getMemberGroupList());
- MemberGroup *mg;
- while ((mg=mgli.current()))
+ if (membersHaveSpecificType(mg->members(),type))
{
- if (membersHaveSpecificType(mg->members(),type))
+ //printf("mg->header=%s\n",mg->header().data());
+ bool hasHeader=mg->header()!="[NOHEADER]";
+ ol.startMemberGroupHeader(hasHeader);
+ if (hasHeader)
{
- //printf("mg->header=%s\n",mg->header().data());
- bool hasHeader=mg->header()!="[NOHEADER]";
- ol.startMemberGroupHeader(hasHeader);
- if (hasHeader)
- {
- ol.parseText(mg->header());
- }
- ol.endMemberGroupHeader();
- if (!mg->documentation().isEmpty())
- {
- //printf("Member group has docs!\n");
- ol.startMemberGroupDocs();
- ol.generateDoc("[generated]",-1,0,0,mg->documentation()+"\n",FALSE,FALSE);
- ol.endMemberGroupDocs();
- }
- ol.startMemberGroup();
- //printf("--- mg->writePlainDeclarations ---\n");
- VhdlDocGen::writePlainVHDLDeclarations(mg->members(),ol,cd,nd,fd,gd,type);
- ol.endMemberGroup(hasHeader);
+ ol.parseText(mg->header());
}
- ++mgli;
+ ol.endMemberGroupHeader();
+ if (!mg->documentation().isEmpty())
+ {
+ //printf("Member group has docs!\n");
+ ol.startMemberGroupDocs();
+ ol.generateDoc("[generated]",-1,0,0,mg->documentation()+"\n",FALSE,FALSE,
+ 0,FALSE,FALSE,Config_getBool(MARKDOWN_SUPPORT));
+ ol.endMemberGroupDocs();
+ }
+ ol.startMemberGroup();
+ //printf("--- mg->writePlainDeclarations ---\n");
+ VhdlDocGen::writePlainVHDLDeclarations(mg->members(),ol,cd,nd,fd,gd,type);
+ ol.endMemberGroup(hasHeader);
}
}
}// writeVHDLDeclarations
@@ -2377,9 +2268,9 @@ void VhdlDocGen::writeStringLink(const MemberDef *mdef,QCString mem, OutputList&
-void VhdlDocGen::writeSource(const MemberDef *mdef,OutputList& ol,const QCString & cname)
+void VhdlDocGen::writeSource(const MemberDefMutable *mdef,OutputList& ol,const QCString & cname)
{
- CodeParserInterface &intf = Doxygen::parserManager->getCodeParser(".vhd");
+ auto intf = Doxygen::parserManager->getCodeParser(".vhd");
// pIntf->resetCodeParserState();
QCString codeFragment=mdef->documentation();
@@ -2404,8 +2295,8 @@ void VhdlDocGen::writeSource(const MemberDef *mdef,OutputList& ol,const QCString
codeFragment.prepend("\n");
ol.pushGeneratorState();
- ol.startCodeFragment();
- intf.parseCode( ol, // codeOutIntf
+ ol.startCodeFragment("DoxyCode");
+ intf->parseCode( ol, // codeOutIntf
0, // scope
codeFragment, // input
SrcLangExt_VHDL, // lang
@@ -2419,7 +2310,7 @@ void VhdlDocGen::writeSource(const MemberDef *mdef,OutputList& ol,const QCString
TRUE // show line numbers
);
- ol.endCodeFragment();
+ ol.endCodeFragment("DoxyCode");
ol.popGeneratorState();
if (cname.isEmpty()) return;
@@ -2479,10 +2370,10 @@ void VhdlDocGen::parseUCF(const char* input, Entry* entity,QCString fileName,b
{
if (altera)
{
- int i=temp.find("-name");
- if (i>0)
+ int in=temp.find("-name");
+ if (in>0)
{
- temp=temp.remove(0,i+5);
+ temp=temp.remove(0,in+5);
}
temp.stripPrefix("set_location_assignment");
@@ -2492,8 +2383,8 @@ void VhdlDocGen::parseUCF(const char* input, Entry* entity,QCString fileName,b
else
{
QRegExp ee("[\\s=]");
- int i=temp.find(ee);
- QCString ff=temp.left(i);
+ int in=temp.find(ee);
+ QCString ff=temp.left(in);
temp.stripPrefix(ff.data());
ff.append("#");
if (!temp.isEmpty())
@@ -2593,44 +2484,8 @@ static void writeUCFLink(const MemberDef* mdef,OutputList &ol)
VhdlDocGen::formatString(largs,ol,mdef);
}
-bool VhdlDocGen::findConstraintFile(LayoutNavEntry *lne)
-{
- FileName *fn=Doxygen::inputNameList->getFirst();
- //LayoutNavEntry *cc = LayoutDocManager::instance().rootNavEntry()->find(LayoutNavEntry::Files);
- uint count=Doxygen::inputNameList->count();
- LayoutNavEntry *kk = lne->parent();// find(LayoutNavEntry::Files);
- // LayoutNavEntry *kks = kk->parent();// find(LayoutNavEntry::Files);
- QCString file;
- QCString co("Constraints");
-
- QCString imgExt = getDotImageExtension();
- if (Config_getBool(HAVE_DOT) && imgExt=="svg")
- {
- QCString ov = theTranslator->trDesignOverview();
- QCString ofile("vhdl_design_overview");
- LayoutNavEntry *oo=new LayoutNavEntry( lne,LayoutNavEntry::MainPage,TRUE,ofile,ov,"");
- kk->addChild(oo);
- }
-
- uint i=0;
- while (i<count)
- {
- FileDef *fd=fn->at(i);
- if (fd->name().contains(".ucf") || fd->name().contains(".qsf"))
- {
- file = convertNameToFile(fd->name().data(),FALSE,FALSE);
- LayoutNavEntry *ucf=new LayoutNavEntry(lne,LayoutNavEntry::MainPage,TRUE,file,co,"");
- kk->addChild(ucf);
- break;
- }
- i++;
- }
- return FALSE;
-}
-
-
// for cell_inst : [entity] work.proto [ (label|expr) ]
-QCString VhdlDocGen::parseForConfig(QCString & entity,QCString & arch)
+QCString VhdlDocGen::parseForConfig(QCString & entity,QCString & arch)
{
int index;
QCString label;
@@ -2691,128 +2546,20 @@ QCString VhdlDocGen::parseForBinding(QCString & entity,QCString & arch)
- // find class with upper/lower letters
- ClassDef* VhdlDocGen::findVhdlClass(const char *className )
+// find class with upper/lower letters
+ClassDef* VhdlDocGen::findVhdlClass(const char *className )
+{
+ for (const auto &cd : *Doxygen::classLinkedMap)
{
-
- ClassSDict::Iterator cli(*Doxygen::classSDict);
- ClassDef *cd;
- for (;(cd=cli.current());++cli)
- {
- if (qstricmp(className,cd->name().data())==0)
- {
- return cd;
- }
- }
- return 0;
+ if (qstricmp(className,cd->name().data())==0)
+ {
+ return cd.get();
+ }
}
+ return 0;
+}
-//@param arch bit0:flipflop
-//@param binding e.g entity work.foo(bar)
-//@param label |label0|label1
-// label0:architecture name
-//@param confVhdl of configuration file (identifier::entity_name) or
-// the architecture if isInlineConf TRUE
-//@param isInlineConf
-//@param confN List of configurations
-
-void assignBinding(VhdlConfNode * conf)
-{
- ClassDef *archClass=0,*entClass=0;
- QCString archName;
- QCString arcBind,entBind;
-
- bool others,all;
- entBind=conf->binding;
- QCString conf2=VhdlDocGen::parseForBinding(entBind,arcBind);
-
- if (conf2!="configuration")
- {
- QCString a,c,e;
- if (conf->isInlineConf)
- {
- c=conf->confVhdl;
- e=VhdlDocGen::getIndexWord(conf->confVhdl.data(),0);
- }
- else
- {
- a=VhdlDocGen::getIndexWord(conf->compSpec.data(),0);
- e=VhdlDocGen::getIndexWord(conf->confVhdl.data(),1);
- c=e+"::"+a;
- }
- archClass= VhdlDocGen::findVhdlClass(c.data());//Doxygen::classSDict->find(a.data());
- entClass= VhdlDocGen::findVhdlClass(e.data()); //Doxygen::classSDict->find(e.data());
- }
-
- QCString label=conf->compSpec.lower();
- //label.prepend("|");
-
- if (!archClass)
- {
- // err("architecture %s not found ! ",conf->confVhdl.data());
- return;
- }
-
- archName=archClass->name();
- QCString allOt=VhdlDocGen::getIndexWord(conf->arch.data(),0);
- all=allOt.lower()=="all" ;
- others= allOt.lower()=="others";
-
- for (const auto &cur : getVhdlInstList())
- {
- if (cur->exception.lower()==label || conf->isInlineConf)
- {
- QCString archy;
-
- if (all || others)
- {
- archy=VhdlDocGen::getIndexWord(conf->arch.data(),1);
- }
- else
- {
- archy=conf->arch;
- }
-
- QCString inst1=VhdlDocGen::getIndexWord(archy.data(),0).lower();
- QCString comp=VhdlDocGen::getIndexWord(archy.data(),1).lower();
-
- QCStringList ql=QCStringList::split(",",inst1);
-
- for (uint j=0;j<ql.count();j++)
- {
- QCString archy1,sign1;
- if (all || others)
- {
- archy1=VhdlDocGen::getIndexWord(conf->arch.data(),1);
- sign1=cur->type;
- }
- else
- {
- archy1=comp+":"+ql[j];
- sign1=cur->type+":"+cur->name;
- }
-
- if (archy1==sign1.lower() && !cur->stat)
- {
- // fprintf(stderr," \n label [%s] [%s] [%s]",cur->exception.data(),cur->type.data(),cur->name.data());
- ClassDef *ent= VhdlDocGen::findVhdlClass(entBind.data());//Doxygen::classSDict->find(entBind.data());
-
- if (entClass==0 || ent==0)
- {
- continue;
- }
-
- addInstance(ent,archClass,entClass,cur);
- cur->stat=TRUE;
- break;
- }
- }// for
- }
- }//for each element in instList
-
-}//assignBinding
-
/*
// file foo.vhd
@@ -2848,10 +2595,10 @@ void VhdlDocGen::computeVhdlComponentRelations()
entity=cur->type;
}
- ClassDef *classEntity= VhdlDocGen::findVhdlClass(entity.data());//Doxygen::classSDict->find(entity);
+ ClassDefMutable *classEntity= toClassDefMutable(VhdlDocGen::findVhdlClass(entity.data()));
inst=VhdlDocGen::getIndexWord(cur->args.data(),0);
- ClassDef *cd=Doxygen::classSDict->find(inst);
- ClassDef *ar=Doxygen::classSDict->find(cur->args);
+ ClassDefMutable *cd=toClassDefMutable(Doxygen::classLinkedMap->find(inst));
+ ClassDefMutable *ar=toClassDefMutable(Doxygen::classLinkedMap->find(cur->args));
if (cd==0)
{
@@ -2866,8 +2613,8 @@ void VhdlDocGen::computeVhdlComponentRelations()
}
-static void addInstance(ClassDef* classEntity, ClassDef* ar,
- ClassDef *cd , const std::shared_ptr<Entry> &cur)
+static void addInstance(ClassDefMutable* classEntity, ClassDefMutable* ar,
+ ClassDefMutable *cd , const std::shared_ptr<Entry> &cur)
{
QCString bName,n1;
@@ -2903,14 +2650,14 @@ static void addInstance(ClassDef* classEntity, ClassDef* ar,
ferr:
QCString uu=cur->name;
- MemberDef *md=createMemberDef(
+ std::unique_ptr<MemberDefMutable> md { createMemberDef(
ar->getDefFileName(), cur->startLine,cur->startColumn,
n1,uu,uu, 0,
Public, Normal, cur->stat,Member,
MemberType_Variable,
ArgumentList(),
ArgumentList(),
- "");
+ "") };
if (ar->getOutputFileBase())
{
@@ -2926,37 +2673,41 @@ ferr:
md->setLanguage(SrcLangExt_VHDL);
md->setMemberSpecifiers(VhdlDocGen::INSTANTIATION);
md->setBriefDescription(cur->brief,cur->briefFile,cur->briefLine);
- md->setBodySegment(cur->startLine,-1) ;
+ md->setBodySegment(cur->startLine,cur->startLine,-1) ;
md->setDocumentation(cur->doc.data(),cur->docFile.data(),cur->docLine);
FileDef *fd=ar->getFileDef();
md->setBodyDef(fd);
-
-
- QCString info="Info: Elaborating entity "+n1;
- fd=ar->getFileDef();
- info+=" for hierarchy ";
- QRegExp epr("[|]");
- QCString label=cur->type+":"+cur->write+":"+cur->name;
- label.replace(epr,":");
- info+=label;
- fprintf(stderr,"\n[%s:%d:%s]\n",fd->fileName().data(),cur->startLine,info.data());
-
-
- ar->insertMember(md);
+ //QCString info="Info: Elaborating entity "+n1;
+ //fd=ar->getFileDef();
+ //info+=" for hierarchy ";
+ //QRegExp epr("[|]");
+ //QCString label=cur->type+":"+cur->write+":"+cur->name;
+ //label.replace(epr,":");
+ //info+=label;
+ //fprintf(stderr,"\n[%s:%d:%s]\n",fd->fileName().data(),cur->startLine,info.data());
+ ar->insertMember(md.get());
+ MemberName *mn = Doxygen::functionNameLinkedMap->add(uu);
+ mn->push_back(std::move(md));
}
-void VhdlDocGen::writeRecorUnit(QCString & largs,OutputList& ol ,const MemberDef *mdef)
+void VhdlDocGen::writeRecordUnit(QCString & largs,QCString & ltype,OutputList& ol ,const MemberDefMutable *mdef)
{
- QCStringList ql=QCStringList::split("#",largs,FALSE);
- uint len=ql.count();
- for(uint i=0;i<len;i++)
+ int i=mdef->name().find('~');
+ if (i>0)
{
- QCString n=ql[i];
- VhdlDocGen::formatString(n,ol,mdef);
- if ((len-i)>1) ol.lineBreak();
+ //sets the real record member name
+ const_cast<MemberDefMutable*>(mdef)->setName(mdef->name().left(i).data());
}
+
+ writeLink(mdef,ol);
+ ol.startBold();
+ ol.insertMemberAlign();
+ if (!ltype.isEmpty()){
+ VhdlDocGen::formatString(ltype,ol,mdef);
+ }
+ ol.endBold();
}
@@ -3005,24 +2756,20 @@ bool VhdlDocGen::isSubClass(ClassDef* cd,ClassDef *scd, bool followInstances,int
return FALSE;
}
- if (cd->subClasses())
+ for (const auto &bcd :cd->subClasses())
{
- BaseClassListIterator bcli(*cd->subClasses());
- for ( ; bcli.current() && !found ; ++bcli)
+ const ClassDef *ccd=bcd.classDef;
+ if (!followInstances && ccd->templateMaster()) ccd=ccd->templateMaster();
+ //printf("isSubClass() subclass %s\n",ccd->name().data());
+ if (ccd==scd)
{
- const ClassDef *ccd=bcli.current()->classDef;
- if (!followInstances && ccd->templateMaster()) ccd=ccd->templateMaster();
- //printf("isSubClass() subclass %s\n",ccd->name().data());
- if (ccd==scd)
- {
- found=TRUE;
- }
- else
+ found=TRUE;
+ }
+ else
+ {
+ if (level <256)
{
- if (level <256)
- {
- found=ccd->isBaseClass(scd,followInstances,level+1);
- }
+ found=ccd->isBaseClass(scd,followInstances,level+1);
}
}
}
@@ -3031,35 +2778,33 @@ bool VhdlDocGen::isSubClass(ClassDef* cd,ClassDef *scd, bool followInstances,int
void VhdlDocGen::addBaseClass(ClassDef* cd,ClassDef *ent)
{
- if (cd->baseClasses())
+ BaseClassList bcl = cd->baseClasses();
+ for (auto &bcd : bcl)
{
- BaseClassListIterator bcli(*cd->baseClasses());
- for ( ; bcli.current() ; ++bcli)
+ ClassDef *ccd = bcd.classDef;
+ if (ccd==ent)
{
- ClassDef *ccd=bcli.current()->classDef;
- if (ccd==ent)
+ QCString n = bcd.usedName;
+ int i = n.find('(');
+ if(i<0)
{
- QCString n = bcli.current()->usedName;
- int i = n.find('(');
- if(i<0)
- {
- bcli.current()->usedName.append("(2)");
- return;
- }
- static QRegExp reg("[0-9]+");
- QCString s=n.left(i);
- QCString r=n.right(n.length()-i);
- QCString t=r;
- VhdlDocGen::deleteAllChars(r,')');
- VhdlDocGen::deleteAllChars(r,'(');
- r.setNum(r.toInt()+1);
- t.replace(reg,r.data());
- s.append(t.data());
- bcli.current()->usedName=s;
- bcli.current()->templSpecifiers=t;
+ bcd.usedName.append("(2)");
+ return;
}
+ static QRegExp reg("[0-9]+");
+ QCString s=n.left(i);
+ QCString r=n.right(n.length()-i);
+ QCString t=r;
+ VhdlDocGen::deleteAllChars(r,')');
+ VhdlDocGen::deleteAllChars(r,'(');
+ r.setNum(r.toInt()+1);
+ t.replace(reg,r.data());
+ s.append(t.data());
+ bcd.usedName=s;
+ bcd.templSpecifiers=t;
}
}
+ cd->updateBaseClasses(bcl);
}
@@ -3101,20 +2846,18 @@ void VhdlDocGen::createFlowChart(const MemberDef *mdef)
bool b=readCodeFragment( fd->absFilePath().data(), actualStart,actualEnd,codeFragment);
if (!b) return;
- VHDLOutlineParser &intf =dynamic_cast<VHDLOutlineParser&>(Doxygen::parserManager->getOutlineParser(".vhd"));
+ auto parser { Doxygen::parserManager->getOutlineParser(".vhd") };
VhdlDocGen::setFlowMember(mdef);
std::shared_ptr<Entry> root = std::make_shared<Entry>();
- QStrList filesInSameTu;
- intf.startTranslationUnit("");
- intf.parseInput("",codeFragment.data(),root,FALSE,filesInSameTu);
- intf.finishTranslationUnit();
+ StringVector filesInSameTu;
+ parser->parseInput("",codeFragment.data(),root,nullptr);
}
void VhdlDocGen::resetCodeVhdlParserState()
{
- varMap.clear();
- qli.clear();
- packages.clear();
+ g_varMap.clear();
+ g_classList.clear();
+ g_packages.clear();
}
bool VhdlDocGen::isConstraint(const MemberDef *mdef)
@@ -3225,7 +2968,7 @@ static struct
QList<FlowChart> FlowChart::flowList;
#ifdef DEBUGFLOW
-static QMap<QCString,int> keyMap;
+static std::map<std::string,int> g_keyMap;
#endif
void alignText(QCString & q)
@@ -3336,20 +3079,18 @@ void FlowChart::printFlowTree()
void FlowChart::colTextNodes()
{
- QCString text;
- FlowChart *flno;
+ FlowChart *flno = NULL;
bool found=FALSE;
for (uint j=0;j<flowList.count();j++)
{
FlowChart *flo=flowList.at(j);
if (flo->type&TEXT_NO)
{
- text+=flo->text+'\n';
if (!found)
{
flno=flo;
}
- if (found)
+ else
{
flno->text+=flo->text;
flowList.remove(flo);
@@ -3689,12 +3430,11 @@ void FlowChart::printUmlTree()
}
qcs+="\n";
- QCString & htmlOutDir = Config_getString(HTML_OUTPUT);
+ QCString htmlOutDir = Config_getString(HTML_OUTPUT);
QCString n=convertNameToFileName();
- QCString tmp=htmlOutDir;
- n=PlantumlManager::instance()->writePlantUMLSource(tmp,n,qcs,PlantumlManager::PUML_SVG);
- PlantumlManager::instance()->generatePlantUMLOutput(n.data(),tmp.data(),PlantumlManager::PUML_SVG);
+ n=PlantumlManager::instance()->writePlantUMLSource(htmlOutDir,n,qcs,PlantumlManager::PUML_SVG);
+ PlantumlManager::instance()->generatePlantUMLOutput(n,htmlOutDir,PlantumlManager::PUML_SVG);
}
QCString FlowChart::convertNameToFileName()
@@ -3803,9 +3543,8 @@ void FlowChart::writeFlowChart()
#ifdef DEBUGFLOW
printFlowTree();
#endif
- const MemberDef *p=VhdlDocGen::getFlowMember();
- if (p->isStatic())
+ if (!Config_getString(PLANTUML_JAR_PATH).isEmpty())
{
printUmlTree();
delFlowList();
@@ -3851,7 +3590,7 @@ void FlowChart::writeShape(FTextStream &t,const FlowChart* fl)
#ifdef DEBUGFLOW
QCString qq(getNodeName(fl->id).data());
- keyMap.insert(qq,fl->id);
+ g_keyMap.insert({qq.str(),fl->id});
#endif
bool dec=(fl->type & DECLN);
@@ -3902,7 +3641,7 @@ void FlowChart::writeShape(FTextStream &t,const FlowChart* fl)
else
{
if (fl->text.isEmpty()) return;
- bool var=(fl->type & FlowChart::VARIABLE_NO);
+ bool isVar=(fl->type & FlowChart::VARIABLE_NO);
QCString q=fl->text;
if (exit)
@@ -3918,7 +3657,7 @@ void FlowChart::writeShape(FTextStream &t,const FlowChart* fl)
}
t << "[shape=none margin=0.1, label=<\n";
t << "<TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\" CELLPADDING=\"2\" >\n ";
- if (var)
+ if (isVar)
{
t << "<TR><TD BGCOLOR=\"" << flowCol.varNode << "\" > ";
}
@@ -3940,11 +3679,11 @@ void FlowChart::writeEdge(FTextStream &t,const FlowChart* fl_from,const FlowChar
#ifdef DEBUGFLOW
QCString s1(getNodeName(fl_from->id).data());
QCString s2(getNodeName(fl_to->id).data());
- QMap<QCString, int>::Iterator it = keyMap.find(s1);
- QMap<QCString, int>::Iterator it1 = keyMap.find(s2);
+ auto it = g_keyMap.find(s1.str());
+ auto it1 = g_keyMap.find(s2.str());
// checks if the link is connected to a valid node
- assert(it.key());
- assert(it1.key());
+ assert(it!=g_keyMap.end());
+ assert(it1!=g_keyMap.end());
#endif
writeEdge(t,fl_from->id,fl_to->id,i,b,c);
@@ -3981,7 +3720,7 @@ void FlowChart::writeEdge(FTextStream &t,int fl_from,int fl_to,int i,bool bFrom,
void FlowChart::alignFuncProc( QCString & q,const ArgumentList &al,bool isFunc)
{
- int index=al.size();
+ size_t index=al.size();
if (index==0) return;
int len=q.length()+VhdlDocGen::getFlowMember()->name().length();
@@ -4062,7 +3801,7 @@ int FlowChart::findLabel(int index,QCString &label)
return j;
}
}
- err("could not find label: ",label.data());
+ err("could not find label: %s",label.data());
return 0;
}
@@ -4277,5 +4016,3 @@ void FlowChart::writeFlowLinks(FTextStream &t)
}
} //for
} //writeFlowLinks
-
-
generated by cgit v0.12 at 2024-10-11 21:30:43 (GMT)