This is my patch:

[ 1005891 ] support --with-tsc on PPC

plus a trivial change to settscdump's docstring and a Misc/NEWS entry.

4 files changed, 62 insertions, 2 deletions

diff --git a/Misc/NEWS b/Misc/NEWS
index f6e2faf..632d446 100644
--- a/Misc/NEWS
+++ b/Misc/NEWS
@@ -57,6 +57,9 @@ Tools/Demos
 Build
 -----
 
+- The --with-tsc flag to configure to enable VM profiling with the
+  processor's timestamp counter now works on PPC platforms.
+
 C API
 -----
 
diff --git a/Misc/SpecialBuilds.txt b/Misc/SpecialBuilds.txt
index fc41767..3e05f81 100644
--- a/Misc/SpecialBuilds.txt
+++ b/Misc/SpecialBuilds.txt
@@ -227,3 +227,28 @@ When this symbol is defined, the ceval mainloop and helper functions
 count the number of function calls made.  It keeps detailed statistics
 about what kind of object was called and whether the call hit any of
 the special fast paths in the code.
+
+---------------------------------------------------------------------------
+WITH_TSC                                          introduced for Python 2.4
+
+Super-lowlevel profiling of the interpreter.  When enabled, the sys
+module grows a new function:
+
+settscdump(bool)
+    If true, tell the Python interpreter to dump VM measurements to
+    stderr.  If false, turn off dump.  The measurements are based on the
+    processor's time-stamp counter.
+
+This build option requires a small amount of platform specific code.
+Currently this code is present for linux/x86 and any PowerPC platform
+that uses GCC (i.e. OS X and linux/ppc).
+
+On the PowerPC the rate at which the time base register is incremented
+is not defined by the architecture specification, so you'll need to
+find the manual for your specific processor.  For the 750CX, 750CXe,
+750FX (all sold as the G3) we find:
+
+    The time base counter is clocked at a frequency that is 
+    one-fourth that of the bus clock.
+
+This build is enabled by the --with-tsc flag to configure.
diff --git a/Python/ceval.c b/Python/ceval.c
index 4c9bded..ba452f9 100644
--- a/Python/ceval.c
+++ b/Python/ceval.c
@@ -17,10 +17,38 @@
 #include <ctype.h>
 
 #ifdef WITH_TSC
-#include <asm/msr.h>
 
 typedef unsigned long long uint64;
 
+#if defined(__ppc__) /* <- Don't know if this is the correct symbol; this
+			   section should work for GCC on any PowerPC platform,
+			   irrespective of OS.  POWER?  Who knows :-) */
+
+#define rdtscll(var) ppc_getcounter(&var)
+
+static void
+ppc_getcounter(uint64 *v)
+{
+	register unsigned long tbu, tb, tbu2;
+
+  loop:
+	asm volatile ("mftbu %0" : "=r" (tbu) );
+	asm volatile ("mftb  %0" : "=r" (tb)  );
+	asm volatile ("mftbu %0" : "=r" (tbu2));
+	if (__builtin_expect(tbu != tbu2, 0)) goto loop;
+
+	/* The slightly peculiar way of writing the next lines is 
+	   compiled better by GCC than any other way I tried. */
+	((long*)(v))[0] = tbu;
+	((long*)(v))[1] = tb;
+}
+
+#else /* this section is for linux/x86 */
+
+#include <asm/msr.h>
+
+#endif
+
 void dump_tsc(int opcode, int ticked, uint64 inst0, uint64 inst1, 
 	      uint64 loop0, uint64 loop1, uint64 intr0, uint64 intr1)
 {
@@ -34,6 +62,7 @@ void dump_tsc(int opcode, int ticked, uint64 inst0, uint64 inst1,
 	fprintf(stderr, "opcode=%03d t=%d inst=%06lld loop=%06lld\n",
 		opcode, ticked, inst, loop);
 }
+
 #endif
 
 /* Turn this on if your compiler chokes on the big switch: */
@@ -545,6 +574,9 @@ PyEval_EvalFrame(PyFrameObject *f)
 	rdtscll(inst1);
 	rdtscll(loop0);
 	rdtscll(loop1);
+
+	/* shut up the compiler */
+	opcode = 0;
 #endif
 
 /* Code access macros */
diff --git a/Python/sysmodule.c b/Python/sysmodule.c
index c62b22d..d246a59 100644
--- a/Python/sysmodule.c
+++ b/Python/sysmodule.c
@@ -465,7 +465,7 @@ PyDoc_STRVAR(settscdump_doc,
 \n\
 If true, tell the Python interpreter to dump VM measurements to\n\
 stderr.  If false, turn off dump.  The measurements are based on the\n\
-Pentium time-stamp counter."
+processor's time-stamp counter."
 ); 
 #endif /* TSC */