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| author | CAM Gerlach <CAM.Gerlach@Gerlach.CAM> | 2022-06-09 13:55:06 (GMT) |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-06-09 13:55:06 (GMT) |
| commit | a5ba0f4ebca5020f6c77718a20663e0ac6e194ac (patch) | |
| tree | 955d4afbe49793d5fc3310741bc25f239963e901 /Doc/library/struct.rst | |
| parent | a365dd64c2a1f0d142540d5031003f24986f489f (diff) | |
| download | cpython-a5ba0f4ebca5020f6c77718a20663e0ac6e194ac.zip cpython-a5ba0f4ebca5020f6c77718a20663e0ac6e194ac.tar.gz cpython-a5ba0f4ebca5020f6c77718a20663e0ac6e194ac.tar.bz2 | |
Doc: Update references and examples of old, unsupported OSes and uarches (GH-92791)
Diffstat (limited to 'Doc/library/struct.rst')
| -rw-r--r-- | Doc/library/struct.rst | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/Doc/library/struct.rst b/Doc/library/struct.rst index eccba20..978eeab 100644 --- a/Doc/library/struct.rst +++ b/Doc/library/struct.rst @@ -146,9 +146,10 @@ If the first character is not one of these, ``'@'`` is assumed. Native byte order is big-endian or little-endian, depending on the host system. For example, Intel x86 and AMD64 (x86-64) are little-endian; -Motorola 68000 and PowerPC G5 are big-endian; ARM and Intel Itanium feature -switchable endianness (bi-endian). Use ``sys.byteorder`` to check the -endianness of your system. +IBM z and most legacy architectures are big-endian; +and ARM, RISC-V and IBM Power feature switchable endianness +(bi-endian, though the former two are nearly always little-endian in practice). +Use ``sys.byteorder`` to check the endianness of your system. Native size and alignment are determined using the C compiler's ``sizeof`` expression. This is always combined with native byte order. |