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authorJeremy Hylton <jeremy@alum.mit.edu>2000-11-06 03:43:11 (GMT)
committerJeremy Hylton <jeremy@alum.mit.edu>2000-11-06 03:43:11 (GMT)
commit314e3fb215c4e96a8c5523061623d8439ab4c2dc (patch)
treea7030b813b1740e03474f0d0e6ddd4fb20465a9c /Lib/plat-irix5/DEVICE.py
parenta59ac0a7df57b9081aa08d7e89451e563c58faf9 (diff)
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Change the graph structure to contain the code generator object for
embedded code objects (e.g. functions) rather than the generated code object. This change means that the compiler generates code for everything at the end, rather then generating code for each function as it finds it. Implementation note: _convert_LOAD_CONST in pyassem.py must be change to call getCode(). Other changes follow. Several changes creates extra edges between basic blocks to reflect control flow for loops and exceptions. These missing edges had gone unnoticed because they do not affect the current compilation process. pyassem.py: Add _enable_debug() and _disable_debug() methods that print instructions and blocks to stdout as they are generated. Add edges between blocks for instructions like SETUP_LOOP, FOR_LOOP, etc. Add pruneNext to get rid of bogus edges remaining after unconditional transfer ops (e.g. JUMP_FORWARD) Change repr of Block to omit block length. pycodegen.py: Make sure a new block is started after FOR_LOOP, etc. Change assert implementation to use RAISE_VARARGS 1 when there is no user-specified failure output. misc.py: Implement __contains__ and copy for Set.
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