diff options
author | Jeremy Hylton <jeremy@alum.mit.edu> | 2000-11-06 03:43:11 (GMT) |
---|---|---|
committer | Jeremy Hylton <jeremy@alum.mit.edu> | 2000-11-06 03:43:11 (GMT) |
commit | 314e3fb215c4e96a8c5523061623d8439ab4c2dc (patch) | |
tree | a7030b813b1740e03474f0d0e6ddd4fb20465a9c /Lib/plat-irix6/cddb.py | |
parent | a59ac0a7df57b9081aa08d7e89451e563c58faf9 (diff) | |
download | cpython-314e3fb215c4e96a8c5523061623d8439ab4c2dc.zip cpython-314e3fb215c4e96a8c5523061623d8439ab4c2dc.tar.gz cpython-314e3fb215c4e96a8c5523061623d8439ab4c2dc.tar.bz2 |
Change the graph structure to contain the code generator object for
embedded code objects (e.g. functions) rather than the generated code
object. This change means that the compiler generates code for
everything at the end, rather then generating code for each function
as it finds it. Implementation note: _convert_LOAD_CONST in
pyassem.py must be change to call getCode().
Other changes follow. Several changes creates extra edges between
basic blocks to reflect control flow for loops and exceptions. These
missing edges had gone unnoticed because they do not affect the
current compilation process.
pyassem.py:
Add _enable_debug() and _disable_debug() methods that print
instructions and blocks to stdout as they are generated.
Add edges between blocks for instructions like SETUP_LOOP,
FOR_LOOP, etc.
Add pruneNext to get rid of bogus edges remaining after
unconditional transfer ops (e.g. JUMP_FORWARD)
Change repr of Block to omit block length.
pycodegen.py:
Make sure a new block is started after FOR_LOOP, etc.
Change assert implementation to use RAISE_VARARGS 1 when there is
no user-specified failure output.
misc.py:
Implement __contains__ and copy for Set.
Diffstat (limited to 'Lib/plat-irix6/cddb.py')
0 files changed, 0 insertions, 0 deletions