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authorBenjamin Peterson <benjamin@python.org>2010-05-15 18:00:56 (GMT)
committerBenjamin Peterson <benjamin@python.org>2010-05-15 18:00:56 (GMT)
commit9b140f650f8dbefb2c5047ec8f3470424b8a084a (patch)
tree5cf03f02406534548bc37f904978fcc89b0a2e19 /Lib/test/test_signal.py
parent30b038497bd3e2067e21e9ea2a7e02423999f9ae (diff)
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Merged revisions 81201 via svnmerge from
svn+ssh://pythondev@svn.python.org/python/branches/py3k ................ r81201 | benjamin.peterson | 2010-05-15 12:52:12 -0500 (Sat, 15 May 2010) | 9 lines Merged revisions 81200 via svnmerge from svn+ssh://pythondev@svn.python.org/python/trunk ........ r81200 | benjamin.peterson | 2010-05-15 12:48:55 -0500 (Sat, 15 May 2010) | 1 line use TestCase skip method ........ ................
Diffstat (limited to 'Lib/test/test_signal.py')
-rw-r--r--Lib/test/test_signal.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/Lib/test/test_signal.py b/Lib/test/test_signal.py
index ade339a..a246695 100644
--- a/Lib/test/test_signal.py
+++ b/Lib/test/test_signal.py
@@ -431,8 +431,8 @@ class ItimerTest(unittest.TestCase):
if signal.getitimer(self.itimer) == (0.0, 0.0):
break # sig_vtalrm handler stopped this itimer
else: # Issue 8424
- raise unittest.SkipTest("timeout: likely cause: machine too slow "
- "or load too high")
+ self.skipTest("timeout: likely cause: machine too slow or load too "
+ "high")
# virtual itimer should be (0.0, 0.0) now
self.assertEquals(signal.getitimer(self.itimer), (0.0, 0.0))
@@ -454,8 +454,8 @@ class ItimerTest(unittest.TestCase):
if signal.getitimer(self.itimer) == (0.0, 0.0):
break # sig_prof handler stopped this itimer
else: # Issue 8424
- raise unittest.SkipTest("timeout: likely cause: machine too slow "
- "or load too high")
+ self.skipTest("timeout: likely cause: machine too slow or load too "
+ "high")
# profiling itimer should be (0.0, 0.0) now
self.assertEquals(signal.getitimer(self.itimer), (0.0, 0.0))