From dfd01489094204dbffffd49c280e2e3bece2c155 Mon Sep 17 00:00:00 2001 From: "Andrew M. Kuchling" Date: Mon, 22 Feb 2010 15:13:17 +0000 Subject: #6414: clarify description of processor endianness. Text by Alexey Shamrin; I changed 'DEC Alpha' to the more relevant 'Intel Itanium'. --- Doc/library/struct.rst | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Doc/library/struct.rst b/Doc/library/struct.rst index d29bd7b..a115c1d 100644 --- a/Doc/library/struct.rst +++ b/Doc/library/struct.rst @@ -187,9 +187,11 @@ following table: If the first character is not one of these, ``'@'`` is assumed. -Native byte order is big-endian or little-endian, depending on the host system. -For example, Motorola and Sun processors are big-endian; Intel and DEC -processors are little-endian. +Native byte order is big-endian or little-endian, depending on the host +system. For example, Intel x86 and AMD64 (x86-64) are little-endian; +Motorola 68000 and PowerPC G5 are big-endian; ARM and Intel Itanium feature +switchable endianness (bi-endian). Use ``sys.byteorder`` to check the +endianness of your system. Native size and alignment are determined using the C compiler's ``sizeof`` expression. This is always combined with native byte order. -- cgit v0.12