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author | juehv <juehv@tk-jh-frankenstein.tk.informatik.tu-darmstadt.de> | 2016-11-15 16:11:45 (GMT) |
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committer | juehv <juehv@tk-jh-frankenstein.tk.informatik.tu-darmstadt.de> | 2016-11-15 16:11:45 (GMT) |
commit | 535154c7f3d4debcd59dc409797b6c26d01a3952 (patch) | |
tree | 367a3068aedbf4277b0e1daeea352b33d051e68b | |
parent | 199ea1e231427996fe1b519cf0c2fd9639953ead (diff) | |
download | uscxml-535154c7f3d4debcd59dc409797b6c26d01a3952.zip uscxml-535154c7f3d4debcd59dc409797b6c26d01a3952.tar.gz uscxml-535154c7f3d4debcd59dc409797b6c26d01a3952.tar.bz2 |
add manual test script for vhdl code (based on ghdl)
-rw-r--r-- | test/vhdltest/.old/uscxml_vsim_bak.tar | bin | 0 -> 8704 bytes | |||
-rwxr-xr-x | test/vhdltest/manual_test_ghdl.sh | 62 |
2 files changed, 62 insertions, 0 deletions
diff --git a/test/vhdltest/.old/uscxml_vsim_bak.tar b/test/vhdltest/.old/uscxml_vsim_bak.tar Binary files differnew file mode 100644 index 0000000..3a02aad --- /dev/null +++ b/test/vhdltest/.old/uscxml_vsim_bak.tar diff --git a/test/vhdltest/manual_test_ghdl.sh b/test/vhdltest/manual_test_ghdl.sh new file mode 100755 index 0000000..402bbfc --- /dev/null +++ b/test/vhdltest/manual_test_ghdl.sh @@ -0,0 +1,62 @@ +#!/bin/bash + +ME=`basename $0` +DIR="$( cd "$( dirname "$0" )" && pwd )/" + +# TODO generate dirs with CMAKE as absolut path +SCXML_BIN=$DIR"../../build/bin/" +SCXML_TEST=$DIR"../" + +SIM_DIR=$DIR"../../build/simulation/" +VHDL_OUT=${SIM_DIR}vhd/ +SIM_LIB_DIR=${SIM_DIR}scxml/ +VHDL_TB_NAME=tb + +SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do" + +# get arguments +TEST_NUMBER="test144.scxml" +if [ "$1" != "" ] ; then + TEST_NUMBER="$1" +fi + +# init simulation dir +rm -rf $SIM_DIR +mkdir -p $SIM_DIR +mkdir -p $VHDL_OUT + +# Write file +cd $DIR +${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd +#echo "$(cat ${VHDL_OUT}dut.vhd)" +echo "${VHDL_OUT}dut.vhd written" +TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)" + +if [ "$TMP_RESULT" == "ERROR" ] ; then + echo "Error while generating VHDL" + exit -1 +fi + +# compile stuff +cd ${SIM_DIR} +ghdl --clean +ghdl -a -Wa,--32 ${VHDL_OUT}dut.vhd + +if [ $? -eq 0 ] ; then + echo "syntax check ok." +else + echo "syntax check FAILED." + exit -1 +fi + +ghdl -e -Wa,--32 -Wl,-m32 ${VHDL_TB_NAME} + +if [ $? -eq 0 ] ; then + echo "compilation done." +else + echo "compilation FAILED" + exit -1 +fi + +# start simulator +./tb --stop-time=10ms --vcd=foo.vcd |