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authorjuehv <jens@jensheuschkel.de>2016-04-05 15:22:35 (GMT)
committerjuehv <jens@jensheuschkel.de>2016-04-05 15:22:35 (GMT)
commitd4818c30f7f17427ee4f58e93a32f94f4ee45395 (patch)
tree1f5690aa2269f3a0a6d7f0a139d5023f07dbd01b
parentc758e9eb457c2623d70627e3067049ca5903dbe1 (diff)
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add 2 tmp vhdl write scripts
-rw-r--r--src/uscxml/transform/ChartToVHDL.cpp3
-rwxr-xr-xtest/vhdltest/green_write_dut.sh66
-rwxr-xr-xtest/vhdltest/tmp_write_dut.sh66
3 files changed, 133 insertions, 2 deletions
diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp
index dec4406..1bdcafe 100644
--- a/src/uscxml/transform/ChartToVHDL.cpp
+++ b/src/uscxml/transform/ChartToVHDL.cpp
@@ -1267,8 +1267,7 @@ namespace uscxml {
VLINE("in_complete_entry_set_up_" + toStr(i) + "_sig"),
(VOR, optimalEntrysetters, completeEntrysetters)
);
- (VOR, optimalEntrysetters, completeEntrysetters)
- );
+
tree->print(stream);
stream << ";" << std::endl;
diff --git a/test/vhdltest/green_write_dut.sh b/test/vhdltest/green_write_dut.sh
new file mode 100755
index 0000000..615ca8e
--- /dev/null
+++ b/test/vhdltest/green_write_dut.sh
@@ -0,0 +1,66 @@
+#!/bin/bash
+
+ME=`basename $0`
+DIR="$( cd "$( dirname "$0" )" && pwd )/"
+
+SCXML_BIN=$DIR"../../build/bin/"
+SCXML_TEST=$DIR"../"
+
+SIM_DIR=$DIR"../../build/simulation/"
+#INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/
+INSTALL_DIR=""
+VHDL_OUT=${SIM_DIR}vhd/
+SIM_LIB_DIR=${SIM_DIR}scxml/
+
+LIB_CREATE_CMD="${INSTALL_DIR}vlib $SIM_LIB_DIR"
+LIB_MAP_CMD="${INSTALL_DIR}vmap work $SIM_LIB_DIR"
+COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd"
+#SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl"
+SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do"
+
+# get arguments
+TEST_NUMBER="test144.scxml"
+if [ "$1" != "" ] ; then
+ TEST_NUMBER="$1"
+fi
+
+# init simulation dir
+rm -rf $SIM_DIR
+mkdir -p $SIM_DIR
+mkdir -p $VHDL_OUT
+cp ./debug.do $SIM_DIR
+cp ./automation.tcl $SIM_DIR
+#cp ./modelsim.ini $SIM_DIR
+
+# Write file
+cd $DIR
+#${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd
+${SCXML_BIN}uscxml-transform -t vhdl -i /home/juehv/Desktop/green.scxml -o ${VHDL_OUT}dut.vhd
+#echo "$(cat ${VHDL_OUT}dut.vhd)"
+echo "${VHDL_OUT}dut.vhd written"
+TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)"
+
+if [ "$TMP_RESULT" == "ERROR" ] ; then
+ echo "Error while generating VHDL"
+ exit -1
+fi
+
+# map librarys
+cd ${SIM_DIR}
+$LIB_CREATE_CMD
+$LIB_MAP_CMD
+echo "Library mapped"
+
+# compile stuff
+cd ${SIM_DIR}
+${COMPILE_CMD}
+
+if [ $? -eq 0 ] ; then
+ echo "compilation done."
+else
+ echo "compilation failed"
+ exit -1
+fi
+
+# start simulator
+${SIMULATION_CMD}
diff --git a/test/vhdltest/tmp_write_dut.sh b/test/vhdltest/tmp_write_dut.sh
new file mode 100755
index 0000000..2adc680
--- /dev/null
+++ b/test/vhdltest/tmp_write_dut.sh
@@ -0,0 +1,66 @@
+#!/bin/bash
+
+ME=`basename $0`
+DIR="$( cd "$( dirname "$0" )" && pwd )/"
+
+SCXML_BIN=$DIR"../../build/bin/"
+SCXML_TEST=$DIR"../"
+
+SIM_DIR=$DIR"../../build/simulation/"
+#INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/
+INSTALL_DIR=""
+VHDL_OUT=${SIM_DIR}vhd/
+SIM_LIB_DIR=${SIM_DIR}scxml/
+
+LIB_CREATE_CMD="${INSTALL_DIR}vlib $SIM_LIB_DIR"
+LIB_MAP_CMD="${INSTALL_DIR}vmap work $SIM_LIB_DIR"
+COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd"
+#SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl"
+SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do"
+
+# get arguments
+TEST_NUMBER="test144.scxml"
+if [ "$1" != "" ] ; then
+ TEST_NUMBER="$1"
+fi
+
+# init simulation dir
+rm -rf $SIM_DIR
+mkdir -p $SIM_DIR
+mkdir -p $VHDL_OUT
+cp ./debug.do $SIM_DIR
+cp ./automation.tcl $SIM_DIR
+#cp ./modelsim.ini $SIM_DIR
+
+# Write file
+cd $DIR
+${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd
+#${SCXML_BIN}uscxml-transform -t vhdl -i /home/juehv/Desktop/green.scxml -o ${VHDL_OUT}dut.vhd
+#echo "$(cat ${VHDL_OUT}dut.vhd)"
+echo "${VHDL_OUT}dut.vhd written"
+TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)"
+
+if [ "$TMP_RESULT" == "ERROR" ] ; then
+ echo "Error while generating VHDL"
+ exit -1
+fi
+
+# map librarys
+cd ${SIM_DIR}
+$LIB_CREATE_CMD
+$LIB_MAP_CMD
+echo "Library mapped"
+
+# compile stuff
+cd ${SIM_DIR}
+${COMPILE_CMD}
+
+if [ $? -eq 0 ] ; then
+ echo "compilation done."
+else
+ echo "compilation failed"
+ exit -1
+fi
+
+# start simulator
+${SIMULATION_CMD}