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authorjuehv <jens@jensheuschkel.de>2016-03-01 12:47:13 (GMT)
committerjuehv <jens@jensheuschkel.de>2016-03-01 12:47:13 (GMT)
commitb5a6e616415576606f5e7a3125a4faf3c17af465 (patch)
treec8e62b7fac3091f1cfc4db2816fb57fd6fd84dad
parent1bdf058cf07cfd53885c81af4c0c943d3baac4c6 (diff)
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update automation script
-rw-r--r--test/vhdltest/automation.tcl50
-rw-r--r--test/vhdltest/debug.do27
-rwxr-xr-xtest/vhdltest/write_dut.sh39
3 files changed, 108 insertions, 8 deletions
diff --git a/test/vhdltest/automation.tcl b/test/vhdltest/automation.tcl
new file mode 100644
index 0000000..cf2f05b
--- /dev/null
+++ b/test/vhdltest/automation.tcl
@@ -0,0 +1,50 @@
+# simulation time in ms
+echo "step size"
+set step 20
+# time until simulation will be canceled
+echo "timeout after"
+set timeout 15000000
+
+proc runSim {} {
+ # import the global variable step
+ global step
+ global timeout
+ upvar 0 errorMsg_ errorMsg
+ set runtime 0
+
+ # reset simulator
+ restart -force -nowave
+ add wave *
+ set errorMsg "ERROR"
+
+ echo "start simulation"
+
+ # run until state machine is finished
+ set err 0
+ set completed 0
+ while { $err != 1 & $completed != 1 & $runtime < $timeout } {
+ run $step ns
+ set err [examine -time $runtime -binary /testbench/error_o]
+ set completed [examine -time $runtime -binary /testbench/completed_o]
+ set runtime [ expr $runtime + $step]
+ }
+
+ # if running in gui mode, view results
+ view wave
+
+ # export results to cmd line
+ if { $runtime == $timeout } {
+ echo "TIMEOUT"
+ } elseif { $err == 1 } {
+ echo "ERROR"
+ } else {
+ echo "OK"
+ }
+
+}
+
+# start simulation
+runSim
+
+# exit simulator
+exit -force
diff --git a/test/vhdltest/debug.do b/test/vhdltest/debug.do
new file mode 100644
index 0000000..841533f
--- /dev/null
+++ b/test/vhdltest/debug.do
@@ -0,0 +1,27 @@
+# window setup
+view structure
+view signals
+view wave
+
+# wave setup
+add wave -noupdate -divider -height 32 Inputs
+add wave -position insertpoint \
+sim:/tb/dut/clk \
+sim:/tb/dut/rst \
+sim:/tb/dut/en
+
+add wave -noupdate -divider -height 32 Outputs
+add wave -position insertpoint \
+sim:/tb/dut/state_active_*_o \
+sim:/tb/dut/completed_o
+
+add wave -noupdate -divider -height 32 PRIO
+add wave -position insertpoint \
+sim:/tb/dut/stall
+
+add wave -noupdate -divider -height 32 ALL
+add wave -position insertpoint \
+sim:/tb/dut/*
+
+# run simulation
+run 500 ns
diff --git a/test/vhdltest/write_dut.sh b/test/vhdltest/write_dut.sh
index 2329980..aac4469 100755
--- a/test/vhdltest/write_dut.sh
+++ b/test/vhdltest/write_dut.sh
@@ -1,13 +1,22 @@
#!/bin/bash
-SCXML_BIN=/home/juehv/git/uscxml/build/bin/
-SCXML_TEST=/home/juehv/git/uscxml/test/
-SIM_DIR=/home/juehv/modelsim/automated_test/
-INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/
+ME=`basename $0`
+DIR="$( cd "$( dirname "$0" )" && pwd )/"
+
+SCXML_BIN=$DIR"../../build/bin/"
+SCXML_TEST=$DIR"../"
+
+SIM_DIR=$DIR"../../build/simulation/"
+#INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/
+INSTALL_DIR=""
VHDL_OUT=${SIM_DIR}vhd/
+SIM_LIB_DIR=${SIM_DIR}scxml/
-COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd ${VHDL_OUT}testbench.vhd"
-SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl"
+LIB_CREATE_CMD="${INSTALL_DIR}vlib $SIM_LIB_DIR"
+LIB_MAP_CMD="${INSTALL_DIR}vmap work $SIM_LIB_DIR"
+COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd"
+#SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl"
+SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do"
# get arguments
TEST_NUMBER="test144.scxml"
@@ -15,9 +24,18 @@ if [ "$1" != "" ] ; then
TEST_NUMBER="$1"
fi
+# init simulation dir
+rm -rf $SIM_DIR
+mkdir -p $SIM_DIR
+mkdir -p $VHDL_OUT
+cp ./debug.do $SIM_DIR
+cp ./automation.tcl $SIM_DIR
+#cp ./modelsim.ini $SIM_DIR
+
# Write file
+cd $DIR
${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd
-echo "$(cat ${VHDL_OUT}dut.vhd)"
+#echo "$(cat ${VHDL_OUT}dut.vhd)"
echo "${VHDL_OUT}dut.vhd written"
TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)"
@@ -26,11 +44,15 @@ if [ "$TMP_RESULT" == "ERROR" ] ; then
exit -1
fi
+# map librarys
+cd ${SIM_DIR}
+$LIB_CREATE_CMD
+$LIB_MAP_CMD
+echo "Library mapped"
# compile stuff
cd ${SIM_DIR}
${COMPILE_CMD}
-#/home/juehv/altera/13.1/modelsim_ase/bin/vcom ${VHDL_OUT}dut.vhd testbench.vhd
if [ $? -eq 0 ] ; then
echo "compilation done."
@@ -39,4 +61,5 @@ else
exit -1
fi
+# start simulator
${SIMULATION_CMD}