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| author | Stefan Radomski <github@mintwerk.de> | 2016-07-11 12:56:31 (GMT) |
|---|---|---|
| committer | Stefan Radomski <github@mintwerk.de> | 2016-07-11 12:56:31 (GMT) |
| commit | e3b26dfd988c2ec64ad0b1561ce45b5503866d0b (patch) | |
| tree | d5e081ba3ea661726bd92d8e21c1a913581722ee | |
| parent | 5fa85b7377db25a73a2208063e3167e82febe98f (diff) | |
| parent | 9406c52b2515153afe71b8baef721be400fb3582 (diff) | |
| download | uscxml-e3b26dfd988c2ec64ad0b1561ce45b5503866d0b.zip uscxml-e3b26dfd988c2ec64ad0b1561ce45b5503866d0b.tar.gz uscxml-e3b26dfd988c2ec64ad0b1561ce45b5503866d0b.tar.bz2 | |
Merge branch 'master' of github.com:tklab-tud/uscxml
| -rw-r--r-- | apps/uscxml-transform.cpp | 22 | ||||
| -rw-r--r-- | src/uscxml/transform/ChartToVHDL.cpp | 22 |
2 files changed, 17 insertions, 27 deletions
diff --git a/apps/uscxml-transform.cpp b/apps/uscxml-transform.cpp index 6fd1bf7..de0c594 100644 --- a/apps/uscxml-transform.cpp +++ b/apps/uscxml-transform.cpp @@ -291,17 +291,17 @@ int main(int argc, char** argv) { exit(EXIT_SUCCESS); } -// if (outType == "vhdl") { -// if (outputFile.size() == 0 || outputFile == "-") { -// ChartToVHDL::transform(interpreter).writeTo(std::cout); -// } else { -// std::ofstream outStream; -// outStream.open(outputFile.c_str()); -// ChartToVHDL::transform(interpreter).writeTo(outStream); -// outStream.close(); -// } -// exit(EXIT_SUCCESS); -// } + if (outType == "vhdl") { + if (outputFile.size() == 0 || outputFile == "-") { + ChartToVHDL::transform(interpreter).writeTo(std::cout); + } else { + std::ofstream outStream; + outStream.open(outputFile.c_str()); + ChartToVHDL::transform(interpreter).writeTo(outStream); + outStream.close(); + } + exit(EXIT_SUCCESS); + } // if (outType == "pml") { // if (outputFile.size() == 0 || outputFile == "-") { diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 0cc630a..37fa03c 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -1029,16 +1029,11 @@ void ChartToVHDL::writeActiveStateNplusOne(std::ostream & stream) { // DOMElement* state = *stateIter; // TÖDO: is there a case where complete entry set reflects not the next state ? VBranch* tree = (VASSIGN, - // VLINE("state_next_" + toStr(i) + "_sig"), - // (VAND, - // VLINE("in_complete_entry_set_" + toStr(i) + "_sig") , - // (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), (VNOT, VLINE("state_active_" + toStr(i) + "_sig")))) - // ); - VLINE("state_next_" + toStr(i) + "_sig"), - (VOR, - VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), - (VAND, (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig")), VLINE("state_active_" + toStr(i) + "_sig"))) - ); + VLINE("state_next_" + toStr(i) + "_sig"), + (VOR, + VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), + (VAND, (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig")), VLINE("state_active_" + toStr(i) + "_sig")) + ) ); tree->print(stream); stream << ";" << std::endl; @@ -1251,18 +1246,13 @@ void ChartToVHDL::writeCompleteEntrySet(std::ostream & stream) { } } - // @juehv: you had the following block in here, but it is syntactically wrong! - assert(false); -#if 0 VBranch* tree = (VASSIGN, VLINE("in_complete_entry_set_up_" + toStr(i) + "_sig"), (VOR, optimalEntrysetters, completeEntrysetters) ); - (VOR, optimalEntrysetters, completeEntrysetters) - ); tree->print(stream); stream << ";" << std::endl; -#endif + #if 0 stream << "in_complete_entry_set_up_" << toStr(i) << "_sig <= ('0'" << std::endl; |