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| author | Jens Heuschkel <heuschkel@tk.tu-darmstadt.de> | 2016-11-23 10:41:14 (GMT) |
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| committer | Jens Heuschkel <heuschkel@tk.tu-darmstadt.de> | 2016-11-23 10:41:14 (GMT) |
| commit | d74eedbb34c2badf079e3d75687e8737d19f47d5 (patch) | |
| tree | 4da0f65aa6e73a01b39f8eb2901e5adcf81c3027 /src/uscxml | |
| parent | aa540c457872b1cdd6a28df8d84e767684a9c5aa (diff) | |
| download | uscxml-d74eedbb34c2badf079e3d75687e8737d19f47d5.zip uscxml-d74eedbb34c2badf079e3d75687e8737d19f47d5.tar.gz uscxml-d74eedbb34c2badf079e3d75687e8737d19f47d5.tar.bz2 | |
set return statement of tb compatible to ctest
Diffstat (limited to 'src/uscxml')
| -rw-r--r-- | src/uscxml/transform/ChartToVHDL.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 071d863..9228a2d 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -421,6 +421,7 @@ void ChartToVHDL::writeTestbench(std::ostream &stream) { } } + // test observation and exit condition stream << " -- Test observation" << std::endl; stream << " process (clk)" << std::endl; stream << " variable count_clk : integer := 0;" << std::endl; @@ -433,7 +434,7 @@ void ChartToVHDL::writeTestbench(std::ostream &stream) { stream << "_sig = '1') report \"Complted with errors\" severity error;" << std::endl; } stream << " -- stop simulation" << std::endl; - stream << " finish(1);" << std::endl; + stream << " finish(0);" << std::endl; // use 0 for ctest // -- For both STOP and FINISH the STATUS values are those used // -- in the Verilog $finish task // -- 0 prints nothing |