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| author | Jens Heuschkel <heuschkel@tk.tu-darmstadt.de> | 2016-11-16 16:44:51 (GMT) |
|---|---|---|
| committer | Jens Heuschkel <heuschkel@tk.tu-darmstadt.de> | 2016-11-16 16:44:51 (GMT) |
| commit | 6fff21bd785f4ee410192080251348d7228b92b4 (patch) | |
| tree | f8b553861274c6a85c117ec4562ef11392376574 /src | |
| parent | 8b2c44fa1e3caebb79923e1c763eba610979c544 (diff) | |
| download | uscxml-6fff21bd785f4ee410192080251348d7228b92b4.zip uscxml-6fff21bd785f4ee410192080251348d7228b92b4.tar.gz uscxml-6fff21bd785f4ee410192080251348d7228b92b4.tar.bz2 | |
prittyprinter
Diffstat (limited to 'src')
| -rw-r--r-- | src/uscxml/transform/ChartToVHDL.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index b508030..85c8262 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -1296,7 +1296,7 @@ namespace uscxml { continue; // skips <scxml> node } - VContainer descendantCompletion = VAND; //TODO one AND less would produce fancier code + VContainer descendantCompletion = VAND; //TODO one AND less would produce fancier code // if parent is compound if (getParentState(state) != NULL && isCompound(getParentState(state))) { |