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| author | juehv <juehv@tk-jh-frankenstein.tk.informatik.tu-darmstadt.de> | 2016-06-27 09:35:46 (GMT) |
|---|---|---|
| committer | juehv <juehv@tk-jh-frankenstein.tk.informatik.tu-darmstadt.de> | 2016-06-27 09:35:46 (GMT) |
| commit | 9406c52b2515153afe71b8baef721be400fb3582 (patch) | |
| tree | be8d25cb5f655f83adc2105c056b94befa5b3d63 /src | |
| parent | df5a0bc2cc97425fbe2ed3947a3c9192a96a7361 (diff) | |
| download | uscxml-9406c52b2515153afe71b8baef721be400fb3582.zip uscxml-9406c52b2515153afe71b8baef721be400fb3582.tar.gz uscxml-9406c52b2515153afe71b8baef721be400fb3582.tar.bz2 | |
restore vhdl transformation
Diffstat (limited to 'src')
| -rw-r--r-- | src/uscxml/transform/ChartToVHDL.cpp | 22 |
1 files changed, 6 insertions, 16 deletions
diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 0cc630a..37fa03c 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -1029,16 +1029,11 @@ void ChartToVHDL::writeActiveStateNplusOne(std::ostream & stream) { // DOMElement* state = *stateIter; // TÖDO: is there a case where complete entry set reflects not the next state ? VBranch* tree = (VASSIGN, - // VLINE("state_next_" + toStr(i) + "_sig"), - // (VAND, - // VLINE("in_complete_entry_set_" + toStr(i) + "_sig") , - // (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), (VNOT, VLINE("state_active_" + toStr(i) + "_sig")))) - // ); - VLINE("state_next_" + toStr(i) + "_sig"), - (VOR, - VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), - (VAND, (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig")), VLINE("state_active_" + toStr(i) + "_sig"))) - ); + VLINE("state_next_" + toStr(i) + "_sig"), + (VOR, + VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), + (VAND, (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig")), VLINE("state_active_" + toStr(i) + "_sig")) + ) ); tree->print(stream); stream << ";" << std::endl; @@ -1251,18 +1246,13 @@ void ChartToVHDL::writeCompleteEntrySet(std::ostream & stream) { } } - // @juehv: you had the following block in here, but it is syntactically wrong! - assert(false); -#if 0 VBranch* tree = (VASSIGN, VLINE("in_complete_entry_set_up_" + toStr(i) + "_sig"), (VOR, optimalEntrysetters, completeEntrysetters) ); - (VOR, optimalEntrysetters, completeEntrysetters) - ); tree->print(stream); stream << ";" << std::endl; -#endif + #if 0 stream << "in_complete_entry_set_up_" << toStr(i) << "_sig <= ('0'" << std::endl; |