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author | Jens Heuschkel <heuschkel@tk.tu-darmstadt.de> | 2016-11-17 17:02:10 (GMT) |
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committer | Jens Heuschkel <heuschkel@tk.tu-darmstadt.de> | 2016-11-17 17:02:10 (GMT) |
commit | f56d30b7e681effeea3656791961db7481e10ad9 (patch) | |
tree | 6e2a1d4b049b58fd81feddc0080c7616f2633152 /test/vhdl_manual | |
parent | a7c2510fc1af06fa98bb7434bf3065fe71bb5afd (diff) | |
download | uscxml-f56d30b7e681effeea3656791961db7481e10ad9.zip uscxml-f56d30b7e681effeea3656791961db7481e10ad9.tar.gz uscxml-f56d30b7e681effeea3656791961db7481e10ad9.tar.bz2 |
fix some todos in vhdl
Diffstat (limited to 'test/vhdl_manual')
-rw-r--r-- | test/vhdl_manual/.gitignore | 1 | ||||
-rw-r--r-- | test/vhdl_manual/.old/uscxml_vsim_bak.tar | bin | 0 -> 8704 bytes | |||
-rw-r--r-- | test/vhdl_manual/gtkwave_default.tcl | 3 | ||||
-rwxr-xr-x | test/vhdl_manual/manual_test_ghdl.sh | 66 |
4 files changed, 70 insertions, 0 deletions
diff --git a/test/vhdl_manual/.gitignore b/test/vhdl_manual/.gitignore new file mode 100644 index 0000000..333c1e9 --- /dev/null +++ b/test/vhdl_manual/.gitignore @@ -0,0 +1 @@ +logs/ diff --git a/test/vhdl_manual/.old/uscxml_vsim_bak.tar b/test/vhdl_manual/.old/uscxml_vsim_bak.tar Binary files differnew file mode 100644 index 0000000..3a02aad --- /dev/null +++ b/test/vhdl_manual/.old/uscxml_vsim_bak.tar diff --git a/test/vhdl_manual/gtkwave_default.tcl b/test/vhdl_manual/gtkwave_default.tcl new file mode 100644 index 0000000..5b62068 --- /dev/null +++ b/test/vhdl_manual/gtkwave_default.tcl @@ -0,0 +1,3 @@ +set clkl [list] +lappend clkl "$clk" +set num_added [ gtkwave::addSignalsFromList $clkl ] diff --git a/test/vhdl_manual/manual_test_ghdl.sh b/test/vhdl_manual/manual_test_ghdl.sh new file mode 100755 index 0000000..68038c4 --- /dev/null +++ b/test/vhdl_manual/manual_test_ghdl.sh @@ -0,0 +1,66 @@ +#!/bin/bash +# +# https://sourceforge.net/p/umhdl/wiki/Installation%20-%20Linux/ +# https://linux.die.net/man/1/ghdl +# + +ME=`basename $0` +DIR="$( cd "$( dirname "$0" )" && pwd )/" + +# TODO generate dirs with CMAKE as absolut path +SCXML_BIN=$DIR"../../build/bin/" +SCXML_TEST=$DIR"../" + +SIM_DIR=$DIR"../../build/simulation/" +VHDL_OUT=${SIM_DIR}vhd/ +SIM_LIB_DIR=${SIM_DIR}scxml/ +VHDL_TB_NAME=tb + +SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do" + +# get arguments +TEST_NUMBER="test144.scxml" +if [ "$1" != "" ] ; then + TEST_NUMBER="$1" +fi + +# init simulation dir +rm -rf $SIM_DIR +mkdir -p $SIM_DIR +mkdir -p $VHDL_OUT + +# Write file +cd $DIR +${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd +#echo "$(cat ${VHDL_OUT}dut.vhd)" +echo "${VHDL_OUT}dut.vhd written" +TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)" + +if [ "$TMP_RESULT" == "ERROR" ] ; then + echo "Error while generating VHDL" + exit -1 +fi + +# compile stuff +cd ${SIM_DIR} +ghdl --clean +ghdl -a -Wa,--32 ${VHDL_OUT}dut.vhd + +if [ $? -eq 0 ] ; then + echo "syntax check ok." +else + echo "syntax check FAILED." + exit -1 +fi + +ghdl -e -Wa,--32 -Wl,-m32 ${VHDL_TB_NAME} + +if [ $? -eq 0 ] ; then + echo "compilation done." +else + echo "compilation FAILED" + exit -1 +fi + +# start simulator +ghdl -r tb --stop-time=10ms --vcd=tb.vcd |