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author | Stefan Radomski <sradomski@mintwerk.de> | 2016-01-26 08:39:58 (GMT) |
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committer | Stefan Radomski <sradomski@mintwerk.de> | 2016-01-26 08:39:58 (GMT) |
commit | da54846c2ea8cf35c22b70a2a7a53f525df8f0c9 (patch) | |
tree | af25f3da6922e8f114f1020b52e9065564cdc82e /test/vhdltest | |
parent | 18bca76b4f4d81db962e97cfe79611461a8b7e61 (diff) | |
download | uscxml-da54846c2ea8cf35c22b70a2a7a53f525df8f0c9.zip uscxml-da54846c2ea8cf35c22b70a2a7a53f525df8f0c9.tar.gz uscxml-da54846c2ea8cf35c22b70a2a7a53f525df8f0c9.tar.bz2 |
VHDL transformation
Diffstat (limited to 'test/vhdltest')
-rwxr-xr-x | test/vhdltest/write_dut.sh | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/test/vhdltest/write_dut.sh b/test/vhdltest/write_dut.sh new file mode 100755 index 0000000..2329980 --- /dev/null +++ b/test/vhdltest/write_dut.sh @@ -0,0 +1,42 @@ +#!/bin/bash +SCXML_BIN=/home/juehv/git/uscxml/build/bin/ +SCXML_TEST=/home/juehv/git/uscxml/test/ + +SIM_DIR=/home/juehv/modelsim/automated_test/ +INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/ +VHDL_OUT=${SIM_DIR}vhd/ + +COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd ${VHDL_OUT}testbench.vhd" +SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl" + +# get arguments +TEST_NUMBER="test144.scxml" +if [ "$1" != "" ] ; then + TEST_NUMBER="$1" +fi + +# Write file +${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd +echo "$(cat ${VHDL_OUT}dut.vhd)" +echo "${VHDL_OUT}dut.vhd written" +TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)" + +if [ "$TMP_RESULT" == "ERROR" ] ; then + echo "Error while generating VHDL" + exit -1 +fi + + +# compile stuff +cd ${SIM_DIR} +${COMPILE_CMD} +#/home/juehv/altera/13.1/modelsim_ase/bin/vcom ${VHDL_OUT}dut.vhd testbench.vhd + +if [ $? -eq 0 ] ; then + echo "compilation done." +else + echo "compilation failed" + exit -1 +fi + +${SIMULATION_CMD} |