From 686bee5a98d5b64102c81e0718dc08342f2f9076 Mon Sep 17 00:00:00 2001 From: Andreas Gansen Date: Sat, 12 Mar 2016 17:04:56 +0100 Subject: add missing include NameSpacingParser.h --- src/uscxml/plugins/invoker/im/IMInvoker.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/uscxml/plugins/invoker/im/IMInvoker.cpp b/src/uscxml/plugins/invoker/im/IMInvoker.cpp index 91a22e1..f111743 100644 --- a/src/uscxml/plugins/invoker/im/IMInvoker.cpp +++ b/src/uscxml/plugins/invoker/im/IMInvoker.cpp @@ -21,6 +21,7 @@ #include #include "uscxml/UUID.h" #include "uscxml/dom/DOMUtils.h" +#include "uscxml/dom/NameSpacingParser.h" #include #include "uscxml/concurrency/DelayedEventQueue.h" @@ -1405,4 +1406,4 @@ gboolean IMInvoker::purpleDebugIsEnabled(PurpleDebugLevel level, const char *cat } -} \ No newline at end of file +} -- cgit v0.12 From d9abe5a5480dd3f2c0fd0110b02c1a370f5a3b02 Mon Sep 17 00:00:00 2001 From: Andreas Gansen Date: Sun, 13 Mar 2016 15:05:30 +0100 Subject: return reachable targets / valid events as vector --- src/uscxml/Interpreter.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/uscxml/Interpreter.h b/src/uscxml/Interpreter.h index c65c8f7..420e685 100644 --- a/src/uscxml/Interpreter.h +++ b/src/uscxml/Interpreter.h @@ -46,6 +46,8 @@ #include "uscxml/plugins/Invoker.h" #include "uscxml/plugins/ExecutableContent.h" +#include "dom/DOMUtils.h" + #ifndef TIME_BLOCK # ifdef BUILD_PROFILING # include "uscxml/concurrency/Timer.h" @@ -402,6 +404,38 @@ public: virtual void handleDOMEvent(Arabica::DOM::Events::Event& event); + std::vector getReachableTargets() { + + std::vector e; + tthread::lock_guard lock(_mutex); + Arabica::XPath::NodeSet possibleTransitions = DOMUtils::filterChildElements( "transition", _configuration, false); + + for( size_t i = 0; i < possibleTransitions.size(); i++ ) { + Arabica::DOM::Node transitions = possibleTransitions[ i ]; + Arabica::DOM::NamedNodeMap attributes = transitions.getAttributes(); + Arabica::DOM::Node events = attributes.getNamedItem("target"); + e.push_back( std::string( events.getNodeValue() ) ); + } + return e; + + } + + std::vector getValidEvents() { + + std::vector e; + tthread::lock_guard lock(_mutex); + Arabica::XPath::NodeSet possibleTransitions = DOMUtils::filterChildElements( "transition", _configuration, false); + + for( size_t i = 0; i < possibleTransitions.size(); i++ ) { + Arabica::DOM::Node transitions = possibleTransitions[ i ]; + Arabica::DOM::NamedNodeMap attributes = transitions.getAttributes(); + Arabica::DOM::Node events = attributes.getNamedItem("event"); + e.push_back( std::string( events.getNodeValue() ) ); + } + return e; + + } + protected: static void run(void*); // static method for thread to run @@ -589,6 +623,14 @@ public: return _impl->reset(); } + std::vector getReachableTargets() { + return _impl->getReachableTargets(); + } + + std::vector getValidEvents() { + return _impl->getValidEvents(); + } + void start() { return _impl->start(); } @@ -807,6 +849,7 @@ public: Timer timer; #endif + protected: void setInvokeRequest(const InvokeRequest& req) { -- cgit v0.12 From bbc37f3f4a6bb1dfdcfb52f6ca74e301c6fb2aff Mon Sep 17 00:00:00 2001 From: juehv Date: Wed, 16 Mar 2016 11:45:12 +0100 Subject: update automated test file --- test/vhdltest/debug.do | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/test/vhdltest/debug.do b/test/vhdltest/debug.do index ca62e9c..39210fe 100644 --- a/test/vhdltest/debug.do +++ b/test/vhdltest/debug.do @@ -13,6 +13,7 @@ sim:/tb/dut/en add wave -noupdate -divider -height 20 Outputs add wave -position insertpoint \ sim:/tb/dut/state_active_*_o \ +sim:/tb/dut/*_set_*_o \ sim:/tb/dut/completed_o add wave -noupdate -divider -height 20 System @@ -35,11 +36,16 @@ add wave -noupdate -divider -height 20 Transition_Set add wave -position insertpoint \ sim:/tb/dut/in_optimal_transition_set_*_sig -add wave -noupdate -divider -height 20 Event +#add wave -noupdate -divider -height 20 Event_Interface +#add wave -position insertpoint \ +#sim:/tb/ec/*_i \ +#sim:/tb/ec/*_o + +add wave -noupdate -divider -height 20 ALL_EventController add wave -position insertpoint \ -sim:/tb/dut/*event* +sim:/tb/ec/* -add wave -noupdate -divider -height 20 ALL +add wave -noupdate -divider -height 20 ALL_MicroStepper add wave -position insertpoint \ sim:/tb/dut/* -- cgit v0.12 From f358d6906db05bb3a1643dbcda1eeece991278ee Mon Sep 17 00:00:00 2001 From: juehv Date: Wed, 16 Mar 2016 11:45:47 +0100 Subject: more vhdl -- passing test 144 :) --- src/uscxml/transform/ChartToVHDL.cpp | 365 +++++++++++++++++++++++++++++------ 1 file changed, 303 insertions(+), 62 deletions(-) diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 1573bc7..a4be34a 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -170,7 +170,7 @@ namespace uscxml { stream << " downto 0);" << std::endl; std::list eventNames = _eventTrie.getWordsWithPrefix(""); - stream << " type event_type is ( "; + stream << " type event_type is ( hwe_null, "; seperator = ""; for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { @@ -206,6 +206,7 @@ namespace uscxml { stream << "architecture bhv of tb is" << std::endl; stream << std::endl; + // modules stream << " -- Module declaration" << std::endl; stream << " component micro_stepper is" << std::endl; stream << " port (" << std::endl; @@ -221,6 +222,22 @@ namespace uscxml { for (size_t i = 0; i < _states.size(); i++) { Element state(_states[i]); stream << " state_active_" << ATTR(state, "documentOrder") << "_o :out std_logic;" << std::endl; + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << " entry_set_" << ATTR(state, "documentOrder") << "_o :out std_logic;" << std::endl; + } + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << " exit_set_" << ATTR(state, "documentOrder") << "_o :out std_logic;" << std::endl; + } + } + + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { + stream << " transition_set_" << ATTR(transition, "postFixOrder") << "_o :out std_logic;" + << std::endl; + } } stream << " completed_o :out std_logic" << std::endl; @@ -228,10 +245,49 @@ namespace uscxml { stream << " end component;" << std::endl; stream << std::endl; + stream << " component event_controller is" << std::endl; + stream << " port(" << std::endl; + stream << " --inputs" << std::endl; + stream << " clk :in std_logic;" << std::endl; + stream << " rst_i :in std_logic;" << std::endl; + + for (size_t i = 0; i < _states.size(); i++) { + Element state(_states[i]); + stream << " state_active_" << ATTR(state, "documentOrder") + << "_i :in std_logic;" << std::endl; + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << " entry_set_" << ATTR(state, "documentOrder") + << "_i :in std_logic;" << std::endl; + } + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << " exit_set_" << ATTR(state, "documentOrder") + << "_i :in std_logic;" << std::endl; + } + } + + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { + stream << " transition_set_" << ATTR(transition, "postFixOrder") + << "_i :in std_logic;" << std::endl; + } + } + stream << " --outputs" << std::endl; + stream << " micro_stepper_en_o :out std_logic;" << std::endl; + stream << " event_o :out event_type;" << std::endl; + stream << " event_we_o :out std_logic" << std::endl; + // stream << " done_o :out std_logic" << std::endl; + stream << ");" << std::endl; + stream << "end component; " << std::endl; + + // signals stream << " -- input" << std::endl; stream << " signal clk : std_logic := '0';" << std::endl; stream << " signal reset : std_logic;" << std::endl; - stream << " signal next_event_we_i : std_logic := '0';" << std::endl; + stream << " signal dut_enable : std_logic;" << std::endl; + stream << " signal next_event_we_i : std_logic;" << std::endl; stream << " signal next_event_i : event_type;" << std::endl; stream << std::endl; @@ -239,6 +295,32 @@ namespace uscxml { stream << " signal error_o, completed_o : std_logic;" << std::endl; stream << std::endl; + stream << " -- wiring" << std::endl; + for (size_t i = 0; i < _states.size(); i++) { + Element state(_states[i]); + stream << " signal state_active_" << ATTR(state, "documentOrder") + << "_sig : std_logic;" << std::endl; + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << " signal entry_set_" << ATTR(state, "documentOrder") + << "_sig : std_logic;" << std::endl; + } + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << " signal exit_set_" << ATTR(state, "documentOrder") + << "_sig : std_logic;" << std::endl; + } + } + + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { + stream << " signal transition_set_" << ATTR(transition, "postFixOrder") + << "_sig : std_logic;" << std::endl; + } + } + + // wiring stream << "begin" << std::endl; stream << " clk <= not clk after 20 ns; -- 25 MHz clock frequency" << std::endl; stream << " reset <= '1', '0' after 100 ns; -- generates reset signal: --__" << std::endl; @@ -249,7 +331,7 @@ namespace uscxml { stream << " port map (" << std::endl; stream << " clk => clk," << std::endl; stream << " rst_i => reset," << std::endl; - stream << " en => '1'," << std::endl; + stream << " en => dut_enable," << std::endl; stream << std::endl; stream << " next_event_i => next_event_i," << std::endl; @@ -258,13 +340,78 @@ namespace uscxml { for (size_t i = 0; i < _states.size(); i++) { Element state(_states[i]); - stream << " state_active_" << ATTR(state, "documentOrder") << "_o => open," << std::endl; + stream << " state_active_" << ATTR(state, "documentOrder") + << "_o => state_active_" << ATTR(state, "documentOrder") + << "_sig," << std::endl; + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << " entry_set_" << ATTR(state, "documentOrder") + << "_o => entry_set_" << ATTR(state, "documentOrder") + << "_sig," << std::endl; + } + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << " exit_set_" << ATTR(state, "documentOrder") + << "_o => exit_set_" << ATTR(state, "documentOrder") + << "_sig," << std::endl; + } + } + + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { + stream << " transition_set_" << ATTR(transition, "postFixOrder") + << "_o => transition_set_" << ATTR(transition, "postFixOrder") + << "_sig," << std::endl; + } } stream << " completed_o => completed_o" << std::endl; stream << " );" << std::endl; stream << std::endl; + stream << " ec : event_controller" << std::endl; + stream << " port map (" << std::endl; + stream << " clk => clk," << std::endl; + stream << " rst_i => reset," << std::endl; + stream << std::endl; + + stream << " event_o => next_event_i," << std::endl; + stream << " event_we_o => next_event_we_i," << std::endl; + + for (size_t i = 0; i < _states.size(); i++) { + Element state(_states[i]); + stream << " state_active_" << ATTR(state, "documentOrder") + << "_i => state_active_" << ATTR(state, "documentOrder") + << "_sig," << std::endl; + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << " entry_set_" << ATTR(state, "documentOrder") + << "_i => entry_set_" << ATTR(state, "documentOrder") + << "_sig," << std::endl; + } + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << " exit_set_" << ATTR(state, "documentOrder") + << "_i => exit_set_" << ATTR(state, "documentOrder") + << "_sig," << std::endl; + } + } + + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { + stream << " transition_set_" << ATTR(transition, "postFixOrder") + << "_o => transition_set_" << ATTR(transition, "postFixOrder") + << "_sig," << std::endl; + } + } + + stream << " micro_stepper_en_o => dut_enable" << std::endl; + // stream << " done_o => open" << std::endl; + stream << " );" << std::endl; + stream << std::endl; + stream << "end architecture;" << std::endl; stream << "-- END TESTBENCH" << std::endl; @@ -287,7 +434,6 @@ namespace uscxml { stream << " --inputs" << std::endl; stream << " clk :in std_logic;" << std::endl; stream << " rst_i :in std_logic;" << std::endl; - stream << " en :in std_logic;" << std::endl; for (size_t i = 0; i < _states.size(); i++) { Element state(_states[i]); @@ -314,9 +460,9 @@ namespace uscxml { } stream << " --outputs" << std::endl; + stream << " micro_stepper_en_o :out std_logic;" << std::endl; stream << " event_o :out event_type;" << std::endl; - stream << " event_we_o :out std_logic;" << std::endl; - stream << " done_o :out std_logic" << std::endl; + stream << " event_we_o :out std_logic" << std::endl; stream << ");" << std::endl; stream << "end event_controller; " << std::endl; @@ -326,9 +472,11 @@ namespace uscxml { // Add signals and components stream << "signal rst : std_logic;" << std::endl; + stream << "signal micro_stepper_en : std_logic;" << std::endl; + stream << "signal cmpl_buf : std_logic;" << std::endl; + stream << "signal completed_sig : std_logic;" << std::endl; stream << "signal event_bus : event_type;" << std::endl; stream << "signal event_we : std_logic;" << std::endl; - stream << "signal done : std_logic;" << std::endl; for (int i = 0; i < _execContent.size(); i++) { stream << "signal done_" << toStr(i) << "_sig : std_logic;" << std::endl; @@ -337,74 +485,135 @@ namespace uscxml { stream << "-- sequence input line" << std::endl; for (int i = 0; i < _execContent.size(); i++) { - stream << "signal seq_" << toStr(i) << "_sig : std_logic;" << std::endl; + stream << "signal seq_" << toStr(i) << "_sig : std_logic;" << std::endl; } stream << std::endl; stream << "begin" << std::endl; stream << std::endl; - // signal mapping + // system signal mapping stream << "rst <= rst_i;" << std::endl; + stream << "micro_stepper_en_o <= micro_stepper_en;" << std::endl; stream << "event_o <= event_bus;" << std::endl; stream << "event_we_o <= event_we;" << std::endl; - stream << "done_o <= done;" << std::endl; stream << std::endl; + // stall management + stream << "-- stalling microstepper" << std::endl; + // stream << "ms_enable_manager : process (clk, rst) " << std::endl; + // stream << "begin" << std::endl; + // stream << " if rst = '1' then" << std::endl; + // stream << " micro_stepper_en <= '1';" << std::endl; + // stream << " elsif rising_edge(clk) then" << std::endl; + // stream << " " << std::endl; + stream << "micro_stepper_en <= completed_sig or not ( '0' "; + for (size_t i = 0; i < _states.size(); i++) { + Element state(_states[i]); + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << std::endl << " or entry_set_" << ATTR(state, "documentOrder") + << "_i"; + } + + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << std::endl << " or exit_set_" << ATTR(state, "documentOrder") + << "_i"; + } + } + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { + stream << std::endl << " or transition_set_" << ATTR(transition, "postFixOrder") + << "_i"; + } + } + stream << ");" << std::endl; + // stream << " end if;" << std::endl; + // stream << "end process;" << std::endl; + stream << std::endl; + + // write enable management + // stream << "-- write enable for FIFO buffer" << std::endl; + // stream << "event_we <= not rst and ('0'"; + // for (int i = 0; i < _execContent.size(); i++) { + // stream << std::endl << " or start_" << toStr(i) << "_sig"; + // } + // stream << ");" << std::endl; + // stream << std::endl; + // sequential code operation - stream << "ex_content_block : process (clk) " << std::endl; + stream << "-- seq code block " << std::endl; + stream << "ex_content_block : process (clk, rst) " << std::endl; stream << "begin" << std::endl; stream << " if rst = '1' then" << std::endl; for (int i = 0; i < _execContent.size(); i++) { stream << " done_" << toStr(i) << "_sig <= '0';" << std::endl; } + stream << " event_bus <= hwe_null;" << std::endl; + stream << " event_we <= '0';" << std::endl; + stream << " cmpl_buf <= '0';" << std::endl; + stream << " completed_sig <= '0';" << std::endl; stream << " elsif rising_edge(clk) then" << std::endl; + + stream << " if micro_stepper_en = '1' then" << std::endl; + stream << " cmpl_buf <= '0' ;" << std::endl; + stream << " else" << std::endl; + stream << " cmpl_buf <= seq_" << toStr(_execContent.size() - 1) + << "_sig;" << std::endl; + stream << " end if;" << std::endl; + stream << " completed_sig <= cmpl_buf;" << std::endl << std::endl; std::string seperator = " "; for (int i = 0; i < _execContent.size(); i++) { Element exContentElem(_execContent[i]); - if (TAGNAME(_nsInfo.xmlNSPrefix + exContentElem) == "") { - stream << seperator << "if start_" << toStr(i) << "_sig = '1' " - << "and done_" << toStr(i) << "_sig = '0' then" + //TODO if raise + if (TAGNAME(_nsInfo.xmlNSPrefix + exContentElem) == "raise") { + stream << seperator << "if start_" << toStr(i) << "_sig = '1' then" << std::endl; - stream << " event_bus <= hwe_" << ATTR(exContentElem, "event") + //TODO use escape + stream << " event_bus <= hwe_" << ATTR(exContentElem, "event") << ";" << std::endl; - stream << " done_" << toStr(i) << "_sig <= '1';" << std::endl; + stream << " done_" << toStr(i) << "_sig <= '1';" << std::endl; + stream << " event_we <= '1';" << std::endl; seperator = " els"; } } + stream << " elsif micro_stepper_en = '1' then" << std::endl; + for (int i = 0; i < _execContent.size(); i++) { + Element exContentElem(_execContent[i]); + + //TODO if raise + if (TAGNAME(_nsInfo.xmlNSPrefix + exContentElem) == "raise") { + stream << " done_" << toStr(i) << "_sig <= '0';" << std::endl; + } + } + stream << " event_we <= '0';" << std::endl; stream << " end if;" << std::endl; stream << " end if;" << std::endl; stream << "end process;" << std::endl; stream << std::endl; - - // start signal generation - if (_execContent.size() > 0) { - stream << "start_0_sig <= " - << /* TODO find enable line and put here */ "'1'" - << ";" << std::endl; - } - for (size_t i = 0; i < _execContent.size(); i++) { // start lines stream << "start_" << toStr(i) << "_sig <= " << getLineForExecContent(_execContent[i]) << " and " - << "(not done_" << toStr(i) << "_sig )"; + << "not done_" << toStr(i) << "_sig"; if (i != 0) { // if not first element stream << " and seq_" << toStr(i) << "_sig"; } stream << ";" << std::endl; - + } - + + stream << "seq_0_sig <= '1';" << std::endl; for (size_t i = 1; i < _execContent.size(); i++) { - // seq lines - stream << "seq_" << toStr(i) << "_sig <= " - << "done_"<< toStr(i) << "_sig or " + // seq lines (input if process i is in seqence now) + stream << "seq_" << toStr(i) << "_sig <= " + << "done_" << toStr(i - 1) << "_sig or " << "( not " - << getLineForExecContent(_execContent[i]) << " and " - << "seq_" << toStr(i-1) << "_sig )"; - stream << ";" << std::endl; + << getLineForExecContent(_execContent[i - 1]); + stream << " and seq_" << toStr(i - 1) << "_sig"; + stream << " );" << std::endl; } stream << std::endl; @@ -414,13 +623,13 @@ namespace uscxml { std::string ChartToVHDL::getLineForExecContent(const Arabica::DOM::Node& elem) { Arabica::DOM::Node ecBlock = elem; - while(ecBlock) { + while (ecBlock) { if (ecBlock.getNodeType() == Arabica::DOM::Node_base::ELEMENT_NODE) { std::string localName = LOCALNAME_CAST(ecBlock); if (localName == _nsInfo.xmlNSPrefix + "transition") { return "transition_set_" + ATTR_CAST(ecBlock, "postFixOrder") + "_i"; } - + if (localName == _nsInfo.xmlNSPrefix + "onentry") { return "entry_set_" + ATTR_CAST(ecBlock.getParentNode(), "documentOrder") + "_i"; } @@ -436,7 +645,6 @@ namespace uscxml { return ""; } - void ChartToVHDL::writeMicroStepper(std::ostream & stream) { // create MicroStepper top level stream << "-- FSM Logic" << std::endl; @@ -616,8 +824,8 @@ namespace uscxml { stream << "-- system signals" << std::endl; stream << "signal stall : std_logic;" << std::endl; stream << "signal completed_sig : std_logic;" << std::endl; - stream << "signal rst_2 : std_logic;" << std::endl; - stream << "signal rst_1 : std_logic;" << std::endl; + // stream << "signal rst_2 : std_logic;" << std::endl; + // stream << "signal rst_1 : std_logic;" << std::endl; stream << "signal rst : std_logic;" << std::endl; stream << std::endl; @@ -646,6 +854,7 @@ namespace uscxml { stream << "-- transition signals" << std::endl; stream << "signal spontaneous_en : std_logic;" << std::endl; + stream << "signal spontaneous_active : std_logic;" << std::endl; stream << "signal optimal_transition_set_combined_sig : std_logic;" << std::endl; for (size_t i = 0; i < _transitions.size(); i++) { @@ -728,18 +937,19 @@ namespace uscxml { void ChartToVHDL::writeResetHandler(std::ostream & stream) { stream << "-- reset handler" << std::endl; - stream << "rst_proc: process(clk, rst_i)" << std::endl; - stream << "begin" << std::endl; - stream << " if rst_i = '1' then" << std::endl; - stream << " rst_2 <= '1';" << std::endl; - stream << " rst_1 <= '1';" << std::endl; - stream << " rst <= '1';" << std::endl; - stream << " elsif (rising_edge(clk)) then" << std::endl; - stream << " rst_2 <= rst_i;" << std::endl; - stream << " rst_1 <= rst_i;" << std::endl; - stream << " rst <= rst_1;" << std::endl; - stream << " end if;" << std::endl; - stream << "end process;" << std::endl; + stream << "rst <= rst_i;" << std::endl; + // stream << "rst_proc: process(clk, rst_i)" << std::endl; + // stream << "begin" << std::endl; + // stream << " if rst_i = '1' then" << std::endl; + // stream << " rst_2 <= '1';" << std::endl; + // stream << " rst_1 <= '1';" << std::endl; + // stream << " rst <= '1';" << std::endl; + // stream << " elsif (rising_edge(clk)) then" << std::endl; + // stream << " rst_2 <= rst_i;" << std::endl; + // stream << " rst_1 <= rst_i;" << std::endl; + // stream << " rst <= rst_1;" << std::endl; + // stream << " end if;" << std::endl; + // stream << "end process;" << std::endl; stream << std::endl; } @@ -750,7 +960,7 @@ namespace uscxml { stream << "begin" << std::endl; stream << " if rst = '1' then" << std::endl; stream << " spontaneous_en <= '1';" << std::endl; - stream << " elsif rising_edge(clk) then" << std::endl; + stream << " elsif rising_edge(clk) and stall = '0' then" << std::endl; stream << " if spontaneous_en = '1' then" << std::endl; stream << " spontaneous_en <= optimal_transition_set_combined_sig;" << std::endl; stream << " else" << std::endl; @@ -777,9 +987,27 @@ namespace uscxml { stream << " next_event_dequeued <= '0';" << std::endl; - stream << " elsif rising_edge(clk) then" << std::endl; - //TODO - + stream << " elsif falling_edge(clk) then" << std::endl; + stream << " case next_event is " << std::endl; + for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { + stream << " when hwe_" + << eventNameEscape((*eventIter)->value) << " =>" << std::endl; + for (std::list::iterator eventIter2 = eventNames.begin(); eventIter2 != eventNames.end(); eventIter2++) { + stream << " event_" << eventNameEscape((*eventIter2)->value); + if (eventNameEscape((*eventIter)->value) == eventNameEscape((*eventIter2)->value)) { + stream << "_sig <= '1';" << std::endl; + } else { + stream << "_sig <= '0';" << std::endl; + } + } + stream << " next_event_dequeued <= '1';" << std::endl; + } + stream << " when others =>" << std::endl; + for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { + stream << " event_" << eventNameEscape((*eventIter)->value) << "_sig <= '0';" << std::endl; + } + stream << " next_event_dequeued <= '0';" << std::endl; + stream << " end case;" << std::endl; stream << " end if;" << std::endl; stream << "end process;" << std::endl; stream << std::endl; @@ -788,7 +1016,7 @@ namespace uscxml { stream << "next_event <= int_event_output; " << std::endl; stream << "int_event_write_en <= next_event_we_i; " << std::endl; stream << "int_event_input <= next_event_i; " << std::endl; - stream << "int_event_read_en <= not spontaneous_en and not stall; " << std::endl; + stream << "int_event_read_en <= not stall; --not spontaneous_en and " << std::endl; stream << std::endl; } @@ -812,6 +1040,7 @@ namespace uscxml { void ChartToVHDL::writeOptimalTransitionSetSelection(std::ostream & stream) { stream << "-- optimal transition set selection" << std::endl; VContainer optimalTransitions = VOR; + VContainer spontaneoursActive = VOR; for (size_t i = 0; i < _transitions.size(); i++) { Element transition(_transitions[i]); std::string conflicts = ATTR(transition, "conflictBools"); @@ -841,7 +1070,7 @@ namespace uscxml { VLINE("in_optimal_transition_set_" + ATTR(transition, "postFixOrder") + "_sig"), (VAND, (HAS_ATTR(transition, "event") - ? (VNOT, VLINE("spontaneous_en")) + ? (VNOT, VLINE("spontaneous_active")) : (VNOP, VLINE("spontaneous_en"))), VLINE("state_active_" + ATTR(transition, "source") + "_sig"), nameMatchers, @@ -850,7 +1079,12 @@ namespace uscxml { tree->print(stream); stream << ";" << std::endl; - *optimalTransitions += VLINE("in_optimal_transition_set_" + ATTR(transition, "postFixOrder") + "_sig"); + *optimalTransitions += VLINE("in_optimal_transition_set_" + + ATTR(transition, "postFixOrder") + "_sig"); + if (HAS_ATTR(transition, "event") == false) { + *spontaneoursActive += VLINE("in_optimal_transition_set_" + + ATTR(transition, "postFixOrder") + "_sig"); + } } VBranch* tree = (VASSIGN, @@ -859,6 +1093,13 @@ namespace uscxml { tree->print(stream); stream << ";" << std::endl; + + VBranch* tree2 = (VASSIGN, + VLINE("spontaneous_active"), + spontaneoursActive); + + tree2->print(stream); + stream << ";" << std::endl; } void ChartToVHDL::writeExitSet(std::ostream & stream) { @@ -1126,14 +1367,14 @@ namespace uscxml { stream << "state_active_" << ATTR(state, "documentOrder") << "_o <= state_active_" << ATTR(state, "documentOrder") << "_sig;" << std::endl; - if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { - stream << "entry_set_" << ATTR(state, "documentOrder") + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { + stream << "exit_set_" << ATTR(state, "documentOrder") << "_o <= in_exit_set_" << ATTR(state, "documentOrder") << "_sig;" << std::endl; } - if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onexit", state).size() > 0) { - stream << "exit_set_" << ATTR(state, "documentOrder") + if (DOMUtils::filterChildElements(_nsInfo.xmlNSPrefix + "onentry", state).size() > 0) { + stream << "entry_set_" << ATTR(state, "documentOrder") << "_o <= in_entry_set_" << ATTR(state, "documentOrder") << "_sig;" << std::endl; } -- cgit v0.12 From 1cec449a5449e7d3c5c0bca34d83f85ab4a4c2e1 Mon Sep 17 00:00:00 2001 From: Andreas Gansen Date: Wed, 16 Mar 2016 13:42:46 +0100 Subject: renaming getValidEvents() to getEventDescriptors() --- src/uscxml/Interpreter.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/uscxml/Interpreter.h b/src/uscxml/Interpreter.h index 420e685..303e126 100644 --- a/src/uscxml/Interpreter.h +++ b/src/uscxml/Interpreter.h @@ -420,7 +420,7 @@ public: } - std::vector getValidEvents() { + std::vector getEventDescriptors() { std::vector e; tthread::lock_guard lock(_mutex); @@ -627,8 +627,8 @@ public: return _impl->getReachableTargets(); } - std::vector getValidEvents() { - return _impl->getValidEvents(); + std::vector getEventDescriptors() { + return _impl->getEventDescriptors(); } void start() { -- cgit v0.12 From 0e9e267de9ba03dc19b6393dbb679a1bdae3ca54 Mon Sep 17 00:00:00 2001 From: juehv Date: Thu, 17 Mar 2016 14:45:40 +0100 Subject: fix event reset bug --- src/uscxml/transform/ChartToVHDL.cpp | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index a4be34a..9e7366c 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -986,8 +986,27 @@ namespace uscxml { } stream << " next_event_dequeued <= '0';" << std::endl; + stream << " event_consumed <= '0';" << std::endl; - stream << " elsif falling_edge(clk) then" << std::endl; + stream << " elsif falling_edge(clk) and stall = '0' then" << std::endl; + + VContainer eventConsumed = VOR; + for (size_t i = 0; i < _transitions.size(); i++) { + Element transition(_transitions[i]); + + if (HAS_ATTR(transition, "event") == true) { + *eventConsumed += VLINE("in_optimal_transition_set_" + + ATTR(transition, "postFixOrder") + "_sig"); + } + } + + VBranch* tree = (VASSIGN, + VLINE("event_consumed"), + eventConsumed); + tree->print(stream); + stream << ";" << std::endl; + + stream << " if int_event_empty = '0' then " << std::endl; stream << " case next_event is " << std::endl; for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { stream << " when hwe_" @@ -1008,6 +1027,13 @@ namespace uscxml { } stream << " next_event_dequeued <= '0';" << std::endl; stream << " end case;" << std::endl; + stream << " elsif int_event_empty = '1' and event_consumed = '1' then" << std::endl; + + for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { + stream << " event_" << eventNameEscape((*eventIter)->value) << "_sig <= '0';" << std::endl; + } + stream << " next_event_dequeued <= '0';" << std::endl; + stream << " end if;" << std::endl; stream << " end if;" << std::endl; stream << "end process;" << std::endl; stream << std::endl; @@ -1090,14 +1116,12 @@ namespace uscxml { VBranch* tree = (VASSIGN, VLINE("optimal_transition_set_combined_sig"), optimalTransitions); - tree->print(stream); stream << ";" << std::endl; VBranch* tree2 = (VASSIGN, VLINE("spontaneous_active"), spontaneoursActive); - tree2->print(stream); stream << ";" << std::endl; } @@ -1202,15 +1226,15 @@ namespace uscxml { for (size_t j = 0; j < _transitions.size(); j++) { Element transition(_transitions[j]); std::string targetSet = ATTR(transition, "targetBools"); - if (targetSet[i] == '1') { + if (targetSet[i] == '1') {// <- ? TODO Was ist hier der vergleich? *optimalEntrysetters += VLINE("in_optimal_transition_set_" + toStr(j) + "_sig"); } } VContainer completeEntrysetters = VOR; - if (isCompound(state)) { + if (isCompound(state)) { // <- true for scxml? TODO for (size_t j = 0; j < _states.size(); j++) { - if (children[j] != '1') + if (children[j] != '1') // <- ? TODO Was ist hier der vergleich? continue; *completeEntrysetters += VLINE("in_complete_entry_set_up_" + toStr(j) + "_sig"); } -- cgit v0.12 From 4241814c44f413491358f23d48c4193976bb6790 Mon Sep 17 00:00:00 2001 From: juehv Date: Thu, 31 Mar 2016 13:24:52 +0200 Subject: add todos --- src/uscxml/transform/ChartToVHDL.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 9e7366c..7b2bd6f 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -128,7 +128,7 @@ namespace uscxml { // elements.insert(_nsInfo.xmlNSPrefix + "else"); // elements.insert(_nsInfo.xmlNSPrefix + "foreach"); // elements.insert(_nsInfo.xmlNSPrefix + "log"); - // elements.insert(_nsInfo.xmlNSPrefix + "send"); + elements.insert(_nsInfo.xmlNSPrefix + "send"); // elements.insert(_nsInfo.xmlNSPrefix + "assign"); // elements.insert(_nsInfo.xmlNSPrefix + "script"); // elements.insert(_nsInfo.xmlNSPrefix + "cancel"); @@ -402,7 +402,7 @@ namespace uscxml { Element transition(_transitions[i]); if (DOMUtils::filterChildType(Arabica::DOM::Node_base::ELEMENT_NODE, transition).size() > 0) { stream << " transition_set_" << ATTR(transition, "postFixOrder") - << "_o => transition_set_" << ATTR(transition, "postFixOrder") + << "_i => transition_set_" << ATTR(transition, "postFixOrder") << "_sig," << std::endl; } } @@ -567,7 +567,8 @@ namespace uscxml { Element exContentElem(_execContent[i]); //TODO if raise - if (TAGNAME(_nsInfo.xmlNSPrefix + exContentElem) == "raise") { + if (TAGNAME(_nsInfo.xmlNSPrefix + exContentElem) == "raise" || + TAGNAME(_nsInfo.xmlNSPrefix + exContentElem) == "send") { stream << seperator << "if start_" << toStr(i) << "_sig = '1' then" << std::endl; //TODO use escape @@ -1293,7 +1294,7 @@ namespace uscxml { *tmp1 += (VAND, (VNOT, (VAND, - VLINE("state_active" + toStr(j) + "_sig"), + VLINE("state_active_" + toStr(j) + "_sig"), (VNOT, VLINE("in_exit_set_" + toStr(j) + "_sig"))))); -- cgit v0.12 From a35999bbdc44791340daf621d74bac07c2f4f251 Mon Sep 17 00:00:00 2001 From: juehv Date: Thu, 31 Mar 2016 17:58:00 +0200 Subject: fix some S* --- src/uscxml/transform/ChartToVHDL.cpp | 48 +++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 7b2bd6f..286998d 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -128,7 +128,7 @@ namespace uscxml { // elements.insert(_nsInfo.xmlNSPrefix + "else"); // elements.insert(_nsInfo.xmlNSPrefix + "foreach"); // elements.insert(_nsInfo.xmlNSPrefix + "log"); - elements.insert(_nsInfo.xmlNSPrefix + "send"); + elements.insert(_nsInfo.xmlNSPrefix + "send"); // elements.insert(_nsInfo.xmlNSPrefix + "assign"); // elements.insert(_nsInfo.xmlNSPrefix + "script"); // elements.insert(_nsInfo.xmlNSPrefix + "cancel"); @@ -990,23 +990,23 @@ namespace uscxml { stream << " event_consumed <= '0';" << std::endl; stream << " elsif falling_edge(clk) and stall = '0' then" << std::endl; - + VContainer eventConsumed = VOR; for (size_t i = 0; i < _transitions.size(); i++) { Element transition(_transitions[i]); - + if (HAS_ATTR(transition, "event") == true) { *eventConsumed += VLINE("in_optimal_transition_set_" - + ATTR(transition, "postFixOrder") + "_sig"); + + ATTR(transition, "postFixOrder") + "_sig"); } } - + VBranch* tree = (VASSIGN, VLINE("event_consumed"), eventConsumed); tree->print(stream); stream << ";" << std::endl; - + stream << " if int_event_empty = '0' then " << std::endl; stream << " case next_event is " << std::endl; for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { @@ -1029,7 +1029,7 @@ namespace uscxml { stream << " next_event_dequeued <= '0';" << std::endl; stream << " end case;" << std::endl; stream << " elsif int_event_empty = '1' and event_consumed = '1' then" << std::endl; - + for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { stream << " event_" << eventNameEscape((*eventIter)->value) << "_sig <= '0';" << std::endl; } @@ -1052,11 +1052,18 @@ namespace uscxml { for (size_t i = 0; i < _states.size(); i++) { + // TÖDO: is there a case where complete entry set reflects not the next state ? VBranch* tree = (VASSIGN, + // VLINE("state_next_" + toStr(i) + "_sig"), + // (VAND, + // VLINE("in_complete_entry_set_" + toStr(i) + "_sig") , + // (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), (VNOT, VLINE("state_active_" + toStr(i) + "_sig")))) + // ); VLINE("state_next_" + toStr(i) + "_sig"), - (VAND, + (VOR, VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), - (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), (VNOT, VLINE("state_active_" + toStr(i) + "_sig"))))); + (VAND, (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig")), VLINE("state_active_" + toStr(i) + "_sig"))) + ); tree->print(stream); stream << ";" << std::endl; @@ -1175,7 +1182,6 @@ namespace uscxml { void ChartToVHDL::writeDefaultCompletions(std::ostream & stream) { stream << "-- default completion assignments" << std::endl; - std::map, NodeSet > completions; for (size_t i = 0; i < _states.size(); i++) { Element state(_states[i]); @@ -1184,7 +1190,13 @@ namespace uscxml { std::string completion = ATTR(state, "completionBools"); for (size_t j = 0; j < _states.size(); j++) { if (completion[j] == '1') { - completions[Element(_states[j])].push_back(state); + // completions[Element(_states[j])].push_back(state); + completions[state].push_back(Element(_states[j])); + stream << "-- " << toStr(i) << " (" + << ATTR(state, "id") << ") completed through " + << toStr(j) << " (" + << ATTR_CAST(_states[j], "id") << ")" + << std::endl; } } } @@ -1198,7 +1210,8 @@ namespace uscxml { VContainer defaultCompleters = VOR; for (size_t i = 0; i < refs.size(); i++) { - *defaultCompleters += VLINE("in_complete_entry_set_" + toStr(i) + "_sig "); + *defaultCompleters += VLINE("in_complete_entry_set_" + + ATTR_CAST(refs[i],"documentOrder") + "_sig "); } VBranch* tree = (VASSIGN, @@ -1233,7 +1246,8 @@ namespace uscxml { } VContainer completeEntrysetters = VOR; - if (isCompound(state)) { // <- true for scxml? TODO + stream << "--" << state.getNodeName() << std::endl; // for debugging + if (isCompound(state) || isParallel(state)) { // <- true for scxml? TODO for (size_t j = 0; j < _states.size(); j++) { if (children[j] != '1') // <- ? TODO Was ist hier der vergleich? continue; @@ -1243,8 +1257,8 @@ namespace uscxml { VBranch* tree = (VASSIGN, VLINE("in_complete_entry_set_up_" + toStr(i) + "_sig"), - optimalEntrysetters, - completeEntrysetters); + (VOR, optimalEntrysetters, completeEntrysetters) + ); tree->print(stream); stream << ";" << std::endl; @@ -1285,7 +1299,10 @@ namespace uscxml { } VContainer tmp1 = VAND; + // if parent is compound if (isCompound(Element(_states[strTo(parent)]))) { + // TODO: if this state is the default completion of parent + // --> init attr. or if not present first in document order *tmp1 += VLINE("default_completion_" + ATTR(state, "documentOrder") + "_sig"); for (size_t j = 0; j < _states.size(); j++) { @@ -1302,6 +1319,7 @@ namespace uscxml { } + // if parent is parallel if (isParallel(Element(_states[strTo(parent)]))) { *tmp1 += VLINE("in_complete_entry_set_" + toStr(parent) + "_sig"); } -- cgit v0.12 From 520f50ac5aceeaa4db7d766ac764dc5405c91263 Mon Sep 17 00:00:00 2001 From: juehv Date: Tue, 5 Apr 2016 16:30:00 +0200 Subject: update --- src/uscxml/transform/ChartToVHDL.cpp | 74 +++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 7b2bd6f..ca08f0a 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -128,7 +128,7 @@ namespace uscxml { // elements.insert(_nsInfo.xmlNSPrefix + "else"); // elements.insert(_nsInfo.xmlNSPrefix + "foreach"); // elements.insert(_nsInfo.xmlNSPrefix + "log"); - elements.insert(_nsInfo.xmlNSPrefix + "send"); + elements.insert(_nsInfo.xmlNSPrefix + "send"); // elements.insert(_nsInfo.xmlNSPrefix + "assign"); // elements.insert(_nsInfo.xmlNSPrefix + "script"); // elements.insert(_nsInfo.xmlNSPrefix + "cancel"); @@ -990,23 +990,23 @@ namespace uscxml { stream << " event_consumed <= '0';" << std::endl; stream << " elsif falling_edge(clk) and stall = '0' then" << std::endl; - + VContainer eventConsumed = VOR; for (size_t i = 0; i < _transitions.size(); i++) { Element transition(_transitions[i]); - + if (HAS_ATTR(transition, "event") == true) { *eventConsumed += VLINE("in_optimal_transition_set_" - + ATTR(transition, "postFixOrder") + "_sig"); + + ATTR(transition, "postFixOrder") + "_sig"); } } - + VBranch* tree = (VASSIGN, VLINE("event_consumed"), eventConsumed); tree->print(stream); stream << ";" << std::endl; - + stream << " if int_event_empty = '0' then " << std::endl; stream << " case next_event is " << std::endl; for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { @@ -1029,7 +1029,7 @@ namespace uscxml { stream << " next_event_dequeued <= '0';" << std::endl; stream << " end case;" << std::endl; stream << " elsif int_event_empty = '1' and event_consumed = '1' then" << std::endl; - + for (std::list::iterator eventIter = eventNames.begin(); eventIter != eventNames.end(); eventIter++) { stream << " event_" << eventNameEscape((*eventIter)->value) << "_sig <= '0';" << std::endl; } @@ -1052,11 +1052,18 @@ namespace uscxml { for (size_t i = 0; i < _states.size(); i++) { + // TÖDO: is there a case where complete entry set reflects not the next state ? VBranch* tree = (VASSIGN, + // VLINE("state_next_" + toStr(i) + "_sig"), + // (VAND, + // VLINE("in_complete_entry_set_" + toStr(i) + "_sig") , + // (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), (VNOT, VLINE("state_active_" + toStr(i) + "_sig")))) + // ); VLINE("state_next_" + toStr(i) + "_sig"), - (VAND, + (VOR, VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), - (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), (VNOT, VLINE("state_active_" + toStr(i) + "_sig"))))); + (VAND, (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig")), VLINE("state_active_" + toStr(i) + "_sig"))) + ); tree->print(stream); stream << ";" << std::endl; @@ -1166,7 +1173,8 @@ namespace uscxml { VLINE("in_entry_set_" + toStr(i) + "_sig"), (VAND, VLINE("in_complete_entry_set_" + toStr(i) + "_sig"), - (VOR, VLINE("state_active_" + toStr(i) + "_sig"), (VNOT, VLINE("in_exit_set_" + toStr(i) + "_sig"))))); + (VOR, VLINE("in_exit_set_" + toStr(i) + "_sig"), + (VNOT, VLINE("state_active_" + toStr(i) + "_sig"))))); tree->print(stream); stream << ";" << std::endl; @@ -1174,17 +1182,26 @@ namespace uscxml { } void ChartToVHDL::writeDefaultCompletions(std::ostream & stream) { + // TODO direct connect the line in complete entry set (no extra line needed ...) stream << "-- default completion assignments" << std::endl; - + stream << "-- indikates if the state for which I am the def-completion is active" << std::endl; std::map, NodeSet > completions; + for (size_t i = 0; i < _states.size(); i++) { Element state(_states[i]); completions[state]; // initialize other completions to 0 - std::string completion = ATTR(state, "completionBools"); - for (size_t j = 0; j < _states.size(); j++) { - if (completion[j] == '1') { - completions[Element(_states[j])].push_back(state); + // we just need this if parent is a compound state + std::string parent = ATTR(state, "parent"); + if (!parent.empty() + && isCompound(Element(_states[strTo(parent)]))) { + + // Am I default completen ? + std::string completion = ATTR_CAST(_states[strTo(parent)], "completionBools"); + if (completion[i] == '1') { + // Yes? then give me the parent line + completions[state].push_back(Element(_states[strTo(parent)])); + } } } @@ -1198,7 +1215,11 @@ namespace uscxml { VContainer defaultCompleters = VOR; for (size_t i = 0; i < refs.size(); i++) { - *defaultCompleters += VLINE("in_complete_entry_set_" + toStr(i) + "_sig "); + // *defaultCompleters += VLINE("in_complete_entry_set_" + + // TODO: default completion just when state is entered the first time ? + // if yes then we use the following code. If not we have to revert + *defaultCompleters += VLINE("in_entry_set_" + + ATTR_CAST(refs[i], "documentOrder") + "_sig "); } VBranch* tree = (VASSIGN, @@ -1233,9 +1254,10 @@ namespace uscxml { } VContainer completeEntrysetters = VOR; - if (isCompound(state)) { // <- true for scxml? TODO + stream << "--" << state.getNodeName() << std::endl; // for debugging + if (isCompound(state) || isParallel(state)) { // <- true for scxml? TODO for (size_t j = 0; j < _states.size(); j++) { - if (children[j] != '1') // <- ? TODO Was ist hier der vergleich? + if (children[j] != '1') // if is child of state j continue; *completeEntrysetters += VLINE("in_complete_entry_set_up_" + toStr(j) + "_sig"); } @@ -1243,8 +1265,8 @@ namespace uscxml { VBranch* tree = (VASSIGN, VLINE("in_complete_entry_set_up_" + toStr(i) + "_sig"), - optimalEntrysetters, - completeEntrysetters); + (VOR, optimalEntrysetters, completeEntrysetters) + ); tree->print(stream); stream << ";" << std::endl; @@ -1277,7 +1299,6 @@ namespace uscxml { Element state(_states[i]); std::string completion = ATTR(state, "completionBools"); std::string ancestors = ATTR(state, "ancBools"); - std::string children = ATTR(state, "childBools"); std::string parent = ATTR(state, "parent"); if (parent.size() == 0) { @@ -1285,9 +1306,17 @@ namespace uscxml { } VContainer tmp1 = VAND; - if (isCompound(Element(_states[strTo(parent)]))) { + // if parent is compound + if (!parent.empty() && + isCompound(Element(_states[strTo(parent)]))) { + std::string children = ATTR_CAST(_states[strTo(parent)], + "childBools"); + // TODO: do not add default_completion line if not needed + // --> just if this state is the default completion of parent + // --> init attr. or if not present first in document order <-- = completion bool ? *tmp1 += VLINE("default_completion_" + ATTR(state, "documentOrder") + "_sig"); + //TODO check this for (size_t j = 0; j < _states.size(); j++) { if (children[j] != '1') continue; @@ -1302,6 +1331,7 @@ namespace uscxml { } + // if parent is parallel if (isParallel(Element(_states[strTo(parent)]))) { *tmp1 += VLINE("in_complete_entry_set_" + toStr(parent) + "_sig"); } -- cgit v0.12 From d4818c30f7f17427ee4f58e93a32f94f4ee45395 Mon Sep 17 00:00:00 2001 From: juehv Date: Tue, 5 Apr 2016 17:22:35 +0200 Subject: add 2 tmp vhdl write scripts --- src/uscxml/transform/ChartToVHDL.cpp | 3 +- test/vhdltest/green_write_dut.sh | 66 ++++++++++++++++++++++++++++++++++++ test/vhdltest/tmp_write_dut.sh | 66 ++++++++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+), 2 deletions(-) create mode 100755 test/vhdltest/green_write_dut.sh create mode 100755 test/vhdltest/tmp_write_dut.sh diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index dec4406..1bdcafe 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -1267,8 +1267,7 @@ namespace uscxml { VLINE("in_complete_entry_set_up_" + toStr(i) + "_sig"), (VOR, optimalEntrysetters, completeEntrysetters) ); - (VOR, optimalEntrysetters, completeEntrysetters) - ); + tree->print(stream); stream << ";" << std::endl; diff --git a/test/vhdltest/green_write_dut.sh b/test/vhdltest/green_write_dut.sh new file mode 100755 index 0000000..615ca8e --- /dev/null +++ b/test/vhdltest/green_write_dut.sh @@ -0,0 +1,66 @@ +#!/bin/bash + +ME=`basename $0` +DIR="$( cd "$( dirname "$0" )" && pwd )/" + +SCXML_BIN=$DIR"../../build/bin/" +SCXML_TEST=$DIR"../" + +SIM_DIR=$DIR"../../build/simulation/" +#INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/ +INSTALL_DIR="" +VHDL_OUT=${SIM_DIR}vhd/ +SIM_LIB_DIR=${SIM_DIR}scxml/ + +LIB_CREATE_CMD="${INSTALL_DIR}vlib $SIM_LIB_DIR" +LIB_MAP_CMD="${INSTALL_DIR}vmap work $SIM_LIB_DIR" +COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd" +#SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl" +SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do" + +# get arguments +TEST_NUMBER="test144.scxml" +if [ "$1" != "" ] ; then + TEST_NUMBER="$1" +fi + +# init simulation dir +rm -rf $SIM_DIR +mkdir -p $SIM_DIR +mkdir -p $VHDL_OUT +cp ./debug.do $SIM_DIR +cp ./automation.tcl $SIM_DIR +#cp ./modelsim.ini $SIM_DIR + +# Write file +cd $DIR +#${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd +${SCXML_BIN}uscxml-transform -t vhdl -i /home/juehv/Desktop/green.scxml -o ${VHDL_OUT}dut.vhd +#echo "$(cat ${VHDL_OUT}dut.vhd)" +echo "${VHDL_OUT}dut.vhd written" +TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)" + +if [ "$TMP_RESULT" == "ERROR" ] ; then + echo "Error while generating VHDL" + exit -1 +fi + +# map librarys +cd ${SIM_DIR} +$LIB_CREATE_CMD +$LIB_MAP_CMD +echo "Library mapped" + +# compile stuff +cd ${SIM_DIR} +${COMPILE_CMD} + +if [ $? -eq 0 ] ; then + echo "compilation done." +else + echo "compilation failed" + exit -1 +fi + +# start simulator +${SIMULATION_CMD} diff --git a/test/vhdltest/tmp_write_dut.sh b/test/vhdltest/tmp_write_dut.sh new file mode 100755 index 0000000..2adc680 --- /dev/null +++ b/test/vhdltest/tmp_write_dut.sh @@ -0,0 +1,66 @@ +#!/bin/bash + +ME=`basename $0` +DIR="$( cd "$( dirname "$0" )" && pwd )/" + +SCXML_BIN=$DIR"../../build/bin/" +SCXML_TEST=$DIR"../" + +SIM_DIR=$DIR"../../build/simulation/" +#INSTALL_DIR=/home/juehv/altera/13.1/modelsim_ase/bin/ +INSTALL_DIR="" +VHDL_OUT=${SIM_DIR}vhd/ +SIM_LIB_DIR=${SIM_DIR}scxml/ + +LIB_CREATE_CMD="${INSTALL_DIR}vlib $SIM_LIB_DIR" +LIB_MAP_CMD="${INSTALL_DIR}vmap work $SIM_LIB_DIR" +COMPILE_CMD="${INSTALL_DIR}vcom ${VHDL_OUT}dut.vhd" +#SIMULATION_CMD="${INSTALL_DIR}vsim -c scxml_lib.testbench -do automation.tcl" +SIMULATION_CMD="${INSTALL_DIR}vsim work.tb -do debug.do" + +# get arguments +TEST_NUMBER="test144.scxml" +if [ "$1" != "" ] ; then + TEST_NUMBER="$1" +fi + +# init simulation dir +rm -rf $SIM_DIR +mkdir -p $SIM_DIR +mkdir -p $VHDL_OUT +cp ./debug.do $SIM_DIR +cp ./automation.tcl $SIM_DIR +#cp ./modelsim.ini $SIM_DIR + +# Write file +cd $DIR +${SCXML_BIN}uscxml-transform -t vhdl -i ${SCXML_TEST}/w3c/ecma/${TEST_NUMBER} -o ${VHDL_OUT}dut.vhd +#${SCXML_BIN}uscxml-transform -t vhdl -i /home/juehv/Desktop/green.scxml -o ${VHDL_OUT}dut.vhd +#echo "$(cat ${VHDL_OUT}dut.vhd)" +echo "${VHDL_OUT}dut.vhd written" +TMP_RESULT="$(tail -n 1 ${VHDL_OUT}dut.vhd)" + +if [ "$TMP_RESULT" == "ERROR" ] ; then + echo "Error while generating VHDL" + exit -1 +fi + +# map librarys +cd ${SIM_DIR} +$LIB_CREATE_CMD +$LIB_MAP_CMD +echo "Library mapped" + +# compile stuff +cd ${SIM_DIR} +${COMPILE_CMD} + +if [ $? -eq 0 ] ; then + echo "compilation done." +else + echo "compilation failed" + exit -1 +fi + +# start simulator +${SIMULATION_CMD} -- cgit v0.12