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author | powARman <andreas.regel@gmx.de> | 2020-08-03 18:02:45 (GMT) |
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committer | GitHub <noreply@github.com> | 2020-08-03 18:02:45 (GMT) |
commit | 5e293b201f46bd98695bcc92ce2ecaa1f2b15c54 (patch) | |
tree | 80e41cf29284faf03b0ce9aa9de16f9a3e7a6ad3 /src/dotlegendgraph.cpp | |
parent | 97b6582daef5028fd3077a7fc29bd94b393f7ae1 (diff) | |
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Vhdl improvements (ALIAS, translation) (#7813)
* Support VHDL alias constructs.
* Translate class to "Design Unit" for VHDL.
* Fix compile error
* Add new function trDesignUnitDocumentation() to translator.
Adapt english and german translation to use the new function.
Co-authored-by: Andreas Regel <andreas.regel@newayselectronics.com>
Diffstat (limited to 'src/dotlegendgraph.cpp')
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