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authorpowARman <andreas.regel@gmx.de>2020-08-03 18:02:45 (GMT)
committerGitHub <noreply@github.com>2020-08-03 18:02:45 (GMT)
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Vhdl improvements (ALIAS, translation) (#7813)
* Support VHDL alias constructs. * Translate class to "Design Unit" for VHDL. * Fix compile error * Add new function trDesignUnitDocumentation() to translator. Adapt english and german translation to use the new function. Co-authored-by: Andreas Regel <andreas.regel@newayselectronics.com>
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