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authorAndreas Regel <andreas.regel@newayselectronics.com>2018-05-28 11:12:22 (GMT)
committerAndreas Regel <andreas.regel@newayselectronics.com>2018-05-28 11:12:22 (GMT)
commite7fe7109421e75b75c7f8d50dd0e1c165b880eea (patch)
tree12a1a0410e689bacdcbce5541c6c1b2386379011 /src/vhdldocgen.cpp
parent9f7406d151e4f5d021558e97f5d87a0d9cacecf9 (diff)
parent63696c08425fc1662c5e76280e3cc74fb3769d80 (diff)
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Merge branch 'master' into vhdl-localization
# Conflicts: # src/translator.h
Diffstat (limited to 'src/vhdldocgen.cpp')
-rw-r--r--src/vhdldocgen.cpp14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/vhdldocgen.cpp b/src/vhdldocgen.cpp
index fd5e4d7..007c45f 100644
--- a/src/vhdldocgen.cpp
+++ b/src/vhdldocgen.cpp
@@ -2059,19 +2059,21 @@ void VhdlDocGen::writeVHDLDeclaration(MemberDef* mdef,OutputList &ol,
writeLink(mdef,ol);
ol.docify(" ");
- ol.insertMemberAlign();
if (mm==VhdlDocGen::GENERIC)
{
+ ol.insertMemberAlign();
ol.startBold();
VhdlDocGen::formatString(largs,ol,mdef);
ol.endBold();
}
else
{
+ ol.insertMemberAlignLeft(isAnonymous, false);
ol.docify(" ");
ol.startBold();
VhdlDocGen::formatString(ltype,ol,mdef);
ol.endBold();
+ ol.insertMemberAlign();
ol.docify(" ");
VhdlDocGen::formatString(largs,ol,mdef);
}
@@ -2226,11 +2228,11 @@ void VhdlDocGen::writeVHDLDeclaration(MemberDef* mdef,OutputList &ol,
ol.endMemberItem();
if (!mdef->briefDescription().isEmpty() && Config_getBool(BRIEF_MEMBER_DESC) /* && !annMemb */)
{
- QCString s=mdef->briefDescription();
- ol.startMemberDescription(mdef->anchor());
+ QCString s=mdef->briefDescription();
+ ol.startMemberDescription(mdef->anchor(), NULL, mm == VhdlDocGen::PORT);
ol.generateDoc(mdef->briefFile(),mdef->briefLine(),
- mdef->getOuterScope()?mdef->getOuterScope():d,
- mdef,s.data(),TRUE,FALSE,0,TRUE,FALSE);
+ mdef->getOuterScope()?mdef->getOuterScope():d,
+ mdef,s.data(),TRUE,FALSE,0,TRUE,FALSE);
if (detailsVisible)
{
ol.pushGeneratorState();
@@ -2327,7 +2329,7 @@ void VhdlDocGen::writeVHDLDeclarations(MemberList* ml,OutputList &ol,
if (title)
{
- ol.startMemberHeader(title);
+ ol.startMemberHeader(title,type == VhdlDocGen::PORT ? 3 : 2);
ol.parseText(title);
ol.endMemberHeader();
ol.docify(" ");