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| author | Dimitri van Heesch <doxygen@gmail.com> | 2018-12-08 15:55:51 (GMT) |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-08 15:55:51 (GMT) |
| commit | 6f283f9343b39de49b74743afb067071493a0355 (patch) | |
| tree | 6b4d1e063a5b727c072297f011331cbe9d5695d1 /src | |
| parent | 709f0d4a9afc2749073485805d05ba471cc04108 (diff) | |
| parent | 9447c47c5f569dec436e0facef8c0d99fd12943f (diff) | |
| download | Doxygen-6f283f9343b39de49b74743afb067071493a0355.zip Doxygen-6f283f9343b39de49b74743afb067071493a0355.tar.gz Doxygen-6f283f9343b39de49b74743afb067071493a0355.tar.bz2 | |
Merge pull request #6660 from albert-github/feature/bug_vhdl_code
Wrong counting of lines during VHDL code output
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdlcode.l | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vhdlcode.l b/src/vhdlcode.l index ee0731f..aa15183 100644 --- a/src/vhdlcode.l +++ b/src/vhdlcode.l @@ -1505,7 +1505,7 @@ XILINX "INST"|"NET"|"PIN"|"BLKNM"|"BUFG"|"COLLAPSE"|"CPLD"|"COMPGRP"|"CONFI { codifyLines(text,0,FALSE,TRUE); } - g_yyLineNr++; // skip complete line + else g_yyLineNr++; // skip complete line, but count line } else // normal comment { |