summaryrefslogtreecommitdiffstats
path: root/testing
diff options
context:
space:
mode:
authorpowARman <andreas.regel@gmx.de>2020-08-03 18:02:45 (GMT)
committerGitHub <noreply@github.com>2020-08-03 18:02:45 (GMT)
commit5e293b201f46bd98695bcc92ce2ecaa1f2b15c54 (patch)
tree80e41cf29284faf03b0ce9aa9de16f9a3e7a6ad3 /testing
parent97b6582daef5028fd3077a7fc29bd94b393f7ae1 (diff)
downloadDoxygen-5e293b201f46bd98695bcc92ce2ecaa1f2b15c54.zip
Doxygen-5e293b201f46bd98695bcc92ce2ecaa1f2b15c54.tar.gz
Doxygen-5e293b201f46bd98695bcc92ce2ecaa1f2b15c54.tar.bz2
Vhdl improvements (ALIAS, translation) (#7813)
* Support VHDL alias constructs. * Translate class to "Design Unit" for VHDL. * Fix compile error * Add new function trDesignUnitDocumentation() to translator. Adapt english and german translation to use the new function. Co-authored-by: Andreas Regel <andreas.regel@newayselectronics.com>
Diffstat (limited to 'testing')
0 files changed, 0 insertions, 0 deletions