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| author | Stefan Radomski <github@mintwerk.de> | 2017-01-27 21:54:43 (GMT) |
|---|---|---|
| committer | Stefan Radomski <github@mintwerk.de> | 2017-01-27 21:54:43 (GMT) |
| commit | 7f83038a1ef642b883417cc984d1f8ca9f0bc64b (patch) | |
| tree | fd9236e866a06b250992e84bbf41324adf93a9fd /src/uscxml/transform/ChartToVHDL.cpp | |
| parent | b450411ee8f0a57f3ec3909d65ecc289189e2b35 (diff) | |
| download | uscxml-7f83038a1ef642b883417cc984d1f8ca9f0bc64b.zip uscxml-7f83038a1ef642b883417cc984d1f8ca9f0bc64b.tar.gz uscxml-7f83038a1ef642b883417cc984d1f8ca9f0bc64b.tar.bz2 | |
Reactivated BUILD_AS_PLUGINS
Diffstat (limited to 'src/uscxml/transform/ChartToVHDL.cpp')
| -rw-r--r-- | src/uscxml/transform/ChartToVHDL.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/uscxml/transform/ChartToVHDL.cpp b/src/uscxml/transform/ChartToVHDL.cpp index 0a344c8..578b310 100644 --- a/src/uscxml/transform/ChartToVHDL.cpp +++ b/src/uscxml/transform/ChartToVHDL.cpp @@ -766,13 +766,13 @@ void ChartToVHDL::writeEventController(std::ostream &stream) { stream << "signal event_bus : std_logic_vector( " << _eventBitSize << " downto 0);" << std::endl; stream << "signal event_we : std_logic;" << std::endl; - for (int i = 0; i < _execContent.size(); i++) { + for (size_t i = 0; i < _execContent.size(); i++) { stream << "signal done_" << toStr(i) << "_sig : std_logic;" << std::endl; stream << "signal start_" << toStr(i) << "_sig : std_logic;" << std::endl; } stream << "-- sequence input line" << std::endl; - for (int i = 0; i < _execContent.size(); i++) { + for (size_t i = 0; i < _execContent.size(); i++) { stream << "signal seq_" << toStr(i) << "_sig : std_logic;" << std::endl; } stream << std::endl; @@ -838,7 +838,7 @@ void ChartToVHDL::writeEventController(std::ostream &stream) { stream << "ex_content_block : process (clk, rst) " << std::endl; stream << "begin" << std::endl; stream << " if rst = '1' then" << std::endl; - for (int i = 0; i < _execContent.size(); i++) { + for (size_t i = 0; i < _execContent.size(); i++) { stream << " done_" << toStr(i) << "_sig <= '0';" << std::endl; } stream << " event_bus <= (others => '0');" << std::endl; @@ -981,7 +981,7 @@ void ChartToVHDL::writeConditionSolver(std::ostream &stream) { stream << "signal rst : std_logic;" << std::endl; stream << "signal micro_stepper_en : std_logic;" << std::endl; - for (int i = 0; i < _execContent.size(); i++) { + for (size_t i = 0; i < _execContent.size(); i++) { stream << "signal done_" << toStr(i) << "_sig : std_logic;" << std::endl; stream << "signal start_" << toStr(i) << "_sig : std_logic;" << std::endl; } |